82434LX Datasheet, PDF (35/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 PCI Configuration Space Mapped Registers
The PCI Bus defines a slot based ‘‘configuration space’’ that allows each device to contain up to 256 8-bit
configuration registers The PCI specification defines two bus cycles to access the PCI configuration space
Configuration Read and Configuration Write While memory and I O spaces are supported by the Pentium
processor configuration space is not supported For PCI configuration space access the PCMC translates the
Pentium processor I O cycles into PCI configuration cycles Table 1 shows the PCMC configuration space
Address
Offset
00 – 01h
02 – 03h
04 – 05h
06 – 07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10 – 4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59 – 5Fh
60 – 65h
66 – 67h
68 – 6Bh
6C – 6Fh
70h
Register
Symbol
VID
DID
PCICMD
PCISTS
RID
RLPI
SCCD
BCCD
MLT
BIST
HCS
DFC
SCC
HBC
PBC
DRAMC
DRAMT
PAM 6 0
DRB 5 0
DRB 7 6
DRBE
ERRCMD
Table 1 PCMC Configuration Space
Register Name
Vendor Identification
Device Identification
Command Register
Status Register
Revision Identification
Register-Level Programming Interface
Sub-Class Code
Base Class Code
Reserved
Master Latency Timer
Reserved
BIST Register
Reserved
Host CPU Selection
Deturbo Frequency Control
Secondary Cache Control
Host Read Write Buffer Control
PCI Read Write Buffer Control
Reserved
Reserved
DRAM Control
DRAM Timing
Programmable Attribute Map (7 Registers)
DRAM Row Boundary (6 Registers)
DRAM Row Boundary (2 Registers)
DRAM Row Boundary Extension
Reserved
Error Command
Access
RO
RO
RW
RO R WC
RO
RO
RO
RO
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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