82434LX Datasheet, PDF (112/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 4 4 Write Page Hit
Figure 47 depicts a CPU burst write page hit from
DRAM The 82434LX decodes the CPU write cycle
as a DRAM page hit The HIG 4 0 lines are driven
to PCMWQ to post the write to the LBXs In the fig-
ure the write cycle is posted to the CPU-to-Memory
Posted Write Buffer at 4-1-1-1 The write is posted at
4-1-1-1 when the second level cache is configured
for a write-back policy The write is posted to DRAM
at 3-1-1-1 when the second level cache is config-
ured for a write-through policy When the cycle is
decoded as a page hit the PCMC asserts WE and
drives the RCMWQ command on MIG 2 0 to enable
the LBXs to drive the first Qword of the write onto
the memory data lines MEMDRV is then driven to
cause the LBXs to continue to drive the first Qword
for three more clocks CAS 7 0 are then negated
and asserted to perform the writes to the DRAMs as
the MA 1 0 lines advance through the Pentium
processor burst order A single write is similar to the
first write of the burst sequence MIG 2 0 are driven
to NOPM in the clock after CAS 7 0 are asserted
Figure 47 Burst DRAM Write Cycle-Page Hit
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