82434LX Datasheet, PDF (131/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 4 3 Hidden Refresh-Single
Figure 63 depicts a hidden refresh cycle which takes
place after a DRAM read page hit cycle The dia-
gram shows a read cycle completing as the refresh
timing inside the 82434NX PCMC generates a re-
fresh request The cycle is an entire Qword there-
fore a hidden refresh is initiated After the cycle
completes RAS is negated but all eight CAS
lines remain asserted The PCMC then sequentially
asserts the RAS lines starting with RAS1 since
RAS0 was the last active RAS line Each RAS
line is asserted for eight clocks
Figure 63 Hidden Refresh Single
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