82434LX Datasheet, PDF (76/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Table 6 Second Level Cache Latencies with Burst SRAM (82434LX)
Cycle Type
HCLK Count
Burst Read
3-1-1-1
Burst Write
3-1-1-1
Single Read
3
Single Write
3
Pipelined Back to Back Burst Reads
3-1-1-1 1-1-1-1
Read Followed by Pipelined Write
3-1-1-1 2
5 1 2 STANDARD SRAM CACHE CYCLES
(82434LX)
The following sections describe the activity of the
second level cache interface when standard asyn-
chronous SRAMs are used to implement the cache
5 1 2 1 Burst Read (82434LX)
Figure 19 depicts a burst read from the second level
cache with standard SRAMs The CPU initiates the
read cycle by driving address and status onto the
bus and asserting ADS Initially the CA 6 3 are a
propagation delay from the host address lines
A 6 3 Upon sampling W R active and M IO in-
active while ADS is asserted the PCMC asserts
COE to begin a read cycle from the SRAMs CALE
is negated latching the address lines on the SRAM
address inputs allowing the CPU to pipeline a new
address onto the bus CA 4 3 cycle through the
Pentium processor burst order completing the cy-
cle PEN is asserted with the first BRDY and
negated with the last BRDY if parity is implement-
ed on the second level cache data SRAMs and the
MCHK DRAM Second Level Cache Data Parity bit
in the Error Command Register (offset 70h) is set
Figure 20 depicts a burst read from the second level
cache with standard 16- or 18-bit wide dual-byte se-
lect SRAMs A single read cycle from the second
level cache is very similar to the first transfer of a
burst read cycle CALE is not negated throughout
the cycle COE is asserted as shown above but is
negated with BRDY
When the Secondary Cache Allocation (SCA) bit in
the Secondary Cache Control Register is set to 1
the PCMC performs a line fill in the secondary
cache even if the CACHE signal from the CPU is
inactive In this case AHOLD is asserted to prevent
the CPU from beginning a new cycle while the sec-
ond level cache line fill is completing
Back-to-back pipelined burst reads from the second
level cache are shown in the Figure 21
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