82434LX Datasheet, PDF (117/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 5 REFRESH
The refresh of the DRAM array can be performed by
either using RAS -only or CAS -before-RAS re-
fresh cycles When programmed for CAS -before-
RAS refresh hidden refresh cycles are initiated
when possible RAS only refresh can be used with
any type of second level cache configuration (i e no
second level cache is present or either a burst
SRAM or standard SRAM second level cache is im-
plemented) CAS -before-RAS refresh can be en-
abled when either no second level cache is present
or a burst SRAM second level cache is implement-
ed CAS -before-RAS refresh should not be used
when a standard SRAM second level cache is imple-
mented The timing of internally generated refresh
cycles is derived from HCLK and is independent of
any expansion bus refresh cycles
The DRAM controller contains an internal refresh
timer which periodically requests the refresh control
logic to perform either a single refresh or a burst of
four refreshes The single refresh interval is 15 6 ms
The interval for burst of four refreshes is four times
the single refresh interval or 62 4 ms The PCMC is
configured for either single or burst of four refresh
and either RAS -only or CAS -before-RAS re-
fresh via the DRAM Control Register (offset 57h)
To minimize performance impact refresh cycles are
partially deferred until the DRAM interface is idle
The deferment of refresh cycles is limited by the
DRAM maximum RAS low time of 100 ms Refresh
cycles are initiated such that the RAS maximum
low time is never violated
Hidden refresh cycles are run whenever all eight
CAS lines are active when the refresh cycle is in-
ternally requested Normal CAS -before-RAS re-
fresh cycles are run whenever the DRAM interface is
idle when the refresh is requested or when any sub-
set of the CAS lines is inactive as the refresh is
internally requested
To minimize the power surge associated with re-
freshing a large DRAM array the DRAM interface
staggers the assertion of the RAS signals during
both CAS -before-RAS and RAS -only refresh
cycles The order of RAS edges is dependent on
which RAS was most recently asserted prior to the
refresh sequence The RAS that was active will be
the last to be activated during the refresh sequence
All RAS 5 0 lines are negated at the end of re-
fresh cycles thus the first DRAM cycle after a re-
fresh sequence is a row miss
6 1 5 1 RAS -Only Refresh-Single
Figure 52 depicts a RAS -only refresh cycle when
the 82434LX is programmed for single refresh cy-
cles The diagram shows a CPU read cycle complet-
ing as the refresh timing inside the PCMC generates
a refresh request The refresh address is driven on
the MA 10 0 lines Since the CPU cycle was to row
0 RAS0 is negated RAS1 is the first to be as-
serted RAS2 through RAS5 are then asserted
sequentially while RAS0 is driven high precharg-
ing the DRAMs in row 0 RAS0 is then asserted
after RAS5 Each RAS line is asserted for six
host clocks
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