82434LX Datasheet, PDF (21/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
SMIACT
PEN
PCHK
Type
Description
in SYSTEM MANAGEMENT INTERRUPT ACTIVE The Pentium processor asserts
SMIACT to indicate that the processor is operating in System Management Mode
(SMM) When the SMRAM Enable bit in the DRAM Control Register (offset 57h) is set
to 1 the PCMC allows CPU accesses SMRAM as permitted by the SMRAM Space
Register at configuration space offset 72h
out PARITY ENABLE The PEN signal along with the MCE bit in CR4 of the Pentium
processor determines whether a machine check exception will be taken by the CPU as
a result of a parity error on a read cycle The PCMC asserts PEN during DRAM read
cycles if the MCHK on DRAM L2 Cache Data Parity Error Enable bit in the Error
Command Register (offset 70h) is set to 1 The PCMC asserts PEN during CPU
second level cache read cycles if the MCHK on DRAM L2 Cache Data Parity Error
Enable and the L2 Cache Parity Enable bits in the Error Command Register (offset 70h)
are both set to 1
in DATA PARITY CHECK PCHK is sampled by the PCMC to detect parity errors on
CPU read cycles from main memory if the Parity Error Mask Enable bit in the DRAM
Control Register (offset 57h) is reset to 0 PCHK is sampled by the PCMC to detect
parity errors on CPU read cycles from the second level cache if the L2 Cache Parity
Enable bit in the Error Command Register (offset 70h) is set to 1 If incorrect parity was
detected on a data read the PCHK signal is asserted by the Pentium processor two
clocks after BRDY is returned PCHK is asserted for one clock for each clock in
which a parity error was detected
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