82434LX Datasheet, PDF (133/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
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Figure 64 CPU Memory Writes to PCI
7 3 Register Access Cycles
The PCMC contains two registers which are mapped
into I O space the Configuration Space Enable
Register (I O port CF8h) and the Turbo-Reset Con-
trol Register (I O port CF9h) All other internal
PCMC configuration registers are mapped into PCI
configuration space Configuration space must be
enabled by writing a non-zero value to the Key field
in the CSE Register before accesses to these regis-
ters can occur These registers are mapped to loca-
tions C000h through C0FFh in PCI configuration
space If the Key field is programmed with 0h CPU
I O cycles to locations C000h through CFFFh are
forwarded to PCI as ordinary I O cycles Externally
accesses to the I O mapped registers and the con-
figuration space mapped registers use the same bus
transfer protocol Only the PCMC internal decode of
the cycle differs NA is never asserted during
PCMC configuration register or PCI configuration
register access cycles See Section 3 2 PCI Config-
uration Space Mapped Registers for details on the
PCMC configuration space mapping mechanism
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