82434LX Datasheet, PDF (48/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 15 HBC HOST READ WRITE BUFFER CONTROL
Address Offset
Default Value
Attribute
Size
53h
00h
Read Write
8 bits
The HBC Register enables and disables Host-to-main memory and Host-to-PCI posting of write cycles When
posting is enabled the write buffers in the LBX devices post the data that is destined for either main memory
or PCI This register also permits a CPU-to-main memory read cycle to be performed before any pending
posted write data is written to memory
Bits
Description
7 4 RESERVED
3 READ-AROUND-WRITE ENABLE (RAWCM) If enabled the PCMC during a CPU read cycle to
memory where posted write cycles are pending internally snoops the write buffers If the address of
the read differs from the posted write addresses the PCMC initiates the memory read cycle ahead of
the pending posted memory write When RAWCM^e0 the pending posted write is written to memory
before the memory read is performed When RAWCM^e1 the PCMC initiates the memory read ahead
of the pending posted memory writes
2 RESERVED
1 HOST-TO-PCI POSTING ENABLE (HPPE) This bit enables disables the posting of Host-to-PCI
write data in the LBX posting buffers When HPPE^e1 up to 4 Dwords of data can be posted to PCI
HPPE^e0 is reserved Buffering is disabled and each CPU write does not complete until the PCI
transaction completes (TRDY is asserted)
0 82434LX HOST-TO-MEMORY POSTING ENABLE (HMPE) This bit enables disables the posting of
Host-to-main memory write data in the LBX buffers When HMPE^e1 the CPU can post a single write
or a burst write (4 Qwords) The CPU burst write completes at 4-1-1-1 when the second level cache is
in write-back mode and at 3-1-1-1 when the second level cache is either disabled or in write-through
mode When HMPE^e0 Host-to-main memory posting is disabled and the CPU write cycles do not
complete until the data is written to memory
82434NX RESERVED For the 82434NX posting is always enabled and this bit has no affect The
CPU can post a single write or burst write (4 Qwords) HMPE can be set to 0 however the 82434NX
will still allow posting of CPU-to-main memory writes
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