82434LX Datasheet, PDF (34/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 1 4 FORW FORWARD REGISTER
I O Address
Default Value
Attribute
Size
0CFAh
00h
Read Write
8 Bits
This 8-bit register specifies which PCI Bus configuration space is enabled in a multiple PCI Bus configuration
The default value for the FORW Register enables the configuration space of the PCI Bus connected to the
PCMC
Bit
Description
7 0 FORWARD BUS NUMBER R W When this register value is 00h the configuration space of the PCI
Bus connected to the PCMC is enabled and the PCMC initiates a type 0 configuration cycle If the
value of this register is not 00h the PCMC initiates a type 1 configuration cycle to forward the cycle
(via one or more PCI PCI Bridges) to the PCI Bus specified by the contents of this register For non-
zero values bits 7 0 are mapped to AD 23 16 respectively
3 1 5 PMC PCI MECHANISM CONTROL REGISTER
I O Address
Default Value
Access
Size
0CFBh
00h
Read Write
8 bits
The PMC Register selects whether PCI Configuration Access Mechanism 1 or 2 is to be used The register is
located in the CPU I O address space
Bit
Description
7 1 RESERVED
0 PCI CONFIGURATION ACCESS MECHANISM SELECT (PCAMS) R W When PCAMS^e0 the
PCMC uses to PCI Configuration Access Mechanism 2 When PCAMS^e1 the PCMC uses to PCI
Configuration Access Mechanism 1 The CONFADD and CONFDATA Registers are only accessible
when PCAMS^e1
3 1 6 CONFDATA CONFIGURATION DATA REGISTER
I O Address
Default Value
Access
Size
0CFCh
00h
Read Write
32 bits
CONFDATA is a 32 bit read write window into configuration space The portion of configuration space that is
referenced by CONFDATA is determined by the contents of CONFADD
Bit
Description
31 0 CONFIGURATION DATA WINDOW (CDW) R W When using Configuration Access Mechanism
1 if bit 31 of CONFADD is 1 any I O reference that falls in the CONFDATA I O space will be
mapped to configuration space using the contents of CONFADD
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