82434LX Datasheet, PDF (116/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 4 8 Write Cycle 0-Active RAS Mode
When in 0-active RAS mode every CPU cycle to
DRAM results in a RAS and CAS sequence
RAS is always negated after a cycle completes
Figure 51 depicts a CPU Burst Write Cycle to DRAM
where the 82434LX is configured for 0-active RAS
mode The HIG 4 0 lines are driven to PCMWQ to
post the write to the LBXs In the figure the write
cycle is posted to the CPU-to-Memory Posted Write
Buffer at 4-1-1-1 The write is posted at 4-1-1-1
when the second level cache is configured for a
write-back policy The write is posted to DRAM at
3-1-1-1 when the second level cache is configured
for a write-through policy When in 0-active RAS
mode the PCMC defaults to driving the row address
on the MA 10 0 lines The PCMC asserts the RAS
signal for the currently decoded row causing the
DRAMs to latch the row address The PCMC asserts
WE and drives the RCMWQ command on
MIG 2 0 to enable the LBXs to drive the first Qword
of the write onto the memory data lines MEMDRV is
then driven to cause the LBXs to continue to drive
the first Qword The PCMC then switches the
MA 10 0 lines to the column address and asserts
CAS 7 0 to initiate the first write CAS 7 0 are
then negated and asserted to perform the writes to
the DRAMs as the MA 1 0 lines advance through
the Pentium processor burst order A single write is
similar to the first write of the burst sequence
MIG 2 0 are driven to NOPM in the clock after
CAS 7 0 are asserted
Figure 51 Burst DRAM Write Cycle 0-Active RAS Mode
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