82434LX Datasheet, PDF (148/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
When PWROK is negated the PCMC asserts
AHOLD causing the CPU to tri-state the host ad-
dress lines Address lines A 31 29 are sampled by
the PCMC 1 ms after the rising edge of PWROK
The values sampled on A 31 30 are inverted inside
the PCMC and then stored in Configuration Register
52h bits 7 and 6 The A 31 30 strapping options are
depicted in Table 18
Table 18 A 31 30 Strapping Options
A 31 30
Configuration
Register 52h
Bits 7 6
Secondary
Cache Size
11
00
Not Populated
10
01
Reserved
01
10
256 KByte Cache
00
11
512 KByte Cache
The value sampled on A29 is inverted inside the
PCMC and stored in the SRAM Type Bit (bit 5) in the
SCC Register A28 is required to be pulled high for
compatibility with future versions of the PCMC
The PCMC also initiates hard reset when the System
Hard Reset Enable bit in the Turbo-Reset Control
Register (I O address CF9h) is set to 1 and the Re-
set CPU bit toggles from 0 to 1 The PCMC drives
CPURST and PCIRST active for a minimum of
1 ms
Table 19 shows the state of all 82434LX PCMC
output and bi-directional signals during hard reset
During hard reset both CPURST and PCIRST are
asserted When the hard reset is due to PWROK
negation AHOLD is asserted The PCMC samples
the strapping options on the A 31 29 lines 1 ms af-
ter the rising edge of PWROK When hard reset is
initiated via a write to the Turbo-Reset Control Reg-
ister (I O port CF9h) AHOLD remains negated
throughout the hard reset Table 19 also applies to
the 82434NX with the exception of the signals listed
in Section 8 5 82434NX Reset Sequencing
Table 19 82434LX Output and I O Signal States
During Hard Reset
Signal
State
Signal
State
A 31 0
Input
IRDY
Input
AHOLD
High Low KEN
Undefined
BOFF
High
MA 10 0 Undefined
BRDY
High
MDLE
High
CAA 6 3
Undefined MEMACK High-Z
CAB 6 3
Undefined MIG 2 0 Low
CADS 1 0 High
NA
High
CADV 1 0 High
PAR
Input
CALE
High
PEN
High
CAS 7 0
High
PERR
Input
COE 1 0
High
PLOCK
Input
CWE 7 0 High
PIG3
Low
C BE 3 0 Input
PIG 2 0
High
DEVSEL
Input
RAS 5 0 High
DRVPCI
Low
REQ
High-Z
EADS
High
SERR
Input
FRAME
Input
STOP
Input
HIG 4 0
Low
TRDY
Input
INIT
Low
WE
High
INV
Low
Soft reset is initiated by the PCMC in response to
one of two conditions First when the System Hard
Reset Enable bit in the TRC Register is reset to 0
and the Reset CPU bit toggles from 0 to 1 the
PCMC initiates soft reset by asserting INIT for a min-
imum of 2 HCLKs Second the PCMC initiates a soft
reset upon detecting a shutdown cycle from the
CPU In this case the PCMC first broadcasts a shut-
down special cycle on PCI and then asserts INIT for
a minimum of 2 HCLKs
148