82434LX Datasheet, PDF (95/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
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Figure 36 Snoop Hit to Modified Line in Second Level Cache Store in PCI Read Prefetch Buffer
The snoop cycle begins with the PCMC asserting
AHOLD causing the CPU to tri-state the host ad-
dress bus The PCMC drives the DPRA command
enabling the LBXs to drive the snoop address onto
the host address bus The PCMC asserts EADS
INV is not asserted in this case since the snoop cy-
cle is in response to a PCI master read cycle If the
snoop were in response to a PCI master write cycle
then INV would be asserted with EADS Two
clocks after the CPU samples EADS active the
PCMC completes the internal tag lookup In this
case the snoop hit either an unmodified line or a
modified line in the second level cache Since
HITM is inactive the snoop did not hit in the first
level cache The PCMC then schedules a read from
the second level cache to be written to the LBXs
When the CPU burst cycle completes the PCMC ne-
gates the control signals to the second level cache
and asserts CALE opening the cache address latch
and allowing the snoop address to flow through to
the SRAMs The second level cache executes a
read sequence which completes at 3-2-2-2 in the
case of standard SRAMs and 3-1-1-1 in the case of
burst SRAMs During all snoop cycles where a write-
back from the second level cache is required
BOFF is asserted throughout the write-back cycle
This prevents the deadlock that would occur if the
CPU is in the middle of a non-postable write and the
data bus is required for the second level cache
write-back
When using burst SRAMs the read from the SRAMs
follows the Pentium processor burst order However
the memory to PCI read prefetch buffer in the LBXs
is organized as a FIFO and cannot accept data out
of order The SWB0 SWB1 SWB2 and SWB3 com-
mands are used to write data into the buffer in as-
cending order In the above example the PCI master
requests a data item which hits Qword 0 in the
cache thus CA 4 3 count through the following se-
quence 0 1 2 3 (00 01 10 11) If the PCI mas-
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