82434LX Datasheet, PDF (103/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
The 60 MHz and 66 MHz asynchronous SRAM la-
tencies require 15 ns and 12 ns SRAMs respective-
ly The 82434NX PCMC supports asynchronous
SRAMs at 50 MHz The 50 MHz (1 wait-state) tim-
ings require 20 ns SRAMs The burst SRAMs
speeds for 66 MHz 60 MHz and 50 MHz operation
are 8 ns 9 ns and 13 ns clock-to-output valid into a
0 pF test load The SRAM access times listed in this
paragraph are recommendations Actual access
time requirements are a function of system board
layout and routing and should be validated with elec-
trical simulation
5 2 2 STANDARD SRAM CACHE CYCLES
(82434NX)
At 50 60 and 66 MHz the timing of the second level
cache interface with standard asynchronous SRAMs
is identical to the timing in the 82430LX PCIset
Compared to the 82434LX second level cache one
additional connection can be made from the PCMC
to the SRAMs The CCS 1 0 pins in the case of
asynchronous SRAMs are multiplexed onto the
CADV 1 0 pins These are then connected to the
SRAM CS pins The two copies are functionally
identical The two copies are provided for timing rea-
sons These pins allow the PCMC to deselect the
SRAMs putting them into standby mode When a
halt special cycle or a stop grant special cycle is
detected from the CPU the PCMC negates
CCS 1 0 placing the SRAMs into the low power
standby mode The PCMC then generates a halt or
stop grant special cycle on PCI
5 2 3 SECOND LEVEL CACHE STANDBY
When the PCMC detects a halt or stop grant special
cycle from the CPU it first places the second level
cache into the low power stand-by mode by dese-
lecting the SRAMs and then generates a halt or stop
grant special cycle on PCI
With a standard SRAM secondary cache a halt or
stop grant special cycle from the CPU causes the
PCMC to negate CCS 1 0 deselecting the
SRAMs and placing them in a low power standby
mode When the cache is in stand-by mode the first
bus cycle from the CPU brings the cache out of
stand-by and into active mode enabling the SRAMs
to service the cycle in the case of a hit to the cache
The PCMC asserts CCS 1 0 as a propagation de-
lay from the falling edge of ADS CCS 1 0 are
then left asserted until the next halt or stop grant
special cycle is occurs When exiting the powerdown
state the PCMC ignores the Secondary Cache Lea-
doff wait-states bit and executes a 3-2-2-2 read or
4-2-2-2 write in order to allow the SRAMs time to
power up In the case of a read cycle COE 1 0
are asserted in clock two as in the case of ordinary
read cycles
When the SRAMs are powered down the PCMC as-
serts CCS 1 0 when performing a snoop cycle
regardless of whether the cycle hits in the second
level cache The PCMC then negates CCS after
the snoop cycle is complete
With a burst SRAM secondary cache a halt or stop
grant special cycle from the CPU causes the PCMC
to negate CCS and assert CADS 1 0 deselect-
ing the SRAMs placing them in a low power standby
mode CCS is then asserted and is left asserted by
the PCMC Thus when the first cycle is driven from
the CPU the SRAMs sample ADSP and CS ac-
tive placing them in active mode and initiating the
first access
If the SRAMs are required to service a snoop they
are brought out of power-down when the PCMC as-
serts CADS 1 0 The PCMC always asserts
CADS 1 0 with CCS negated after a snoop cy-
cle is complete regardless of whether the SRAMs
were powered down prior to the snoop cycle
5 2 4 SNOOP CYCLES
For snoop operations refer to Section 5 1 82434LX
Cache
5 2 5 FLUSH FLUSH ACKNOWLEDGE AND
WRITE-BACK SPECIAL CYCLES
For flush flush acknowledge and write-back special
cycles refer to Section 5 1 82434LX Cache
103