82434LX Datasheet, PDF (104/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 0 DRAM INTERFACE
This section describes the DRAM interface for the
82434LX DRAM Interface (Section 6 1) and the
82434NX DRAM Interface (Section 6 2) The differ-
ences are in the following areas
1 Increased maximum DRAM memory size to
512 MBytes An extra address line (MA11) has
been added to the 82434NX
2 Two additional RAS lines for a total of eight
(RAS 0 7
3 Addition of 50 MHz host-bus optimized DRAM
timing sets Thus the 82434LX supports 60 and
66 MHz frequencies and the 82434NX supports
50 60 and 66 MHz
6 1 82434LX DRAM Interface
The 82434LX PCMC integrates a high performance
DRAM controller supporting from 2–192 MBytes of
main memory The PCMC generates the RAS
CAS WE and multiplexed addresses for the
DRAM array while the data path to DRAM is provid-
ed by two 82433LX LBXs The DRAM controller in-
terface is fully configurable through a set of control
registers Complete descriptions of these registers
are given in Section 3 0 Register Description A brief
overview of the registers which configure the DRAM
interface is provided in this section
The 82434LX controls a 64-bit memory array (72-bit
including parity) ranging in size from 2 MBytes up to
192 MBytes using industry standard 36-bit wide
memory modules with fast page-mode DRAMs Both
single- and double-sided SIMMs are supported The
eleven multiplexed address lines MA 10 0 allow
the PCMC to support 256K x 36 1M x 36 and
4M x 36 SIMMs The PCMC has six RAS lines en-
abling the support of up to six rows of DRAM Eight
CAS lines allow byte control over the array during
read and write operations The PCMC supports 70
and 60 ns DRAMs The PCMC DRAM interface is
synchronous to the CPU clock and supports page
mode accesses to efficiently transfer data in bursts
of four Qwords
The DRAM interface of the PCMC is configured by
the DRAM Control Mode Register (offset 57h) and
the six DRAM Row Boundary (DRB) Registers (off-
sets 60h – 65h) The DRAM Control Mode Register
contains bits to configure the DRAM interface for
RAS modes and refresh options In addition
DRAM Parity Error Reporting and System Manage-
ment RAM space can be enabled and disabled
When System Management RAM is enabled if
SMIACT from the Pentium processor is not assert-
ed all CPU read and write accesses to SMM memo-
ry are directed to PCI The SMRAM Space Register
at configuration space offset 72h provides additional
control over the SMRAM space The six DRB Regis-
ters define the size of each row in the memory array
enabling the PCMC to assert the proper RAS line
for accesses to the array
CPU-to-Memory write posting and read-around-write
operations are enabled and disabled via the Host
Read Write Buffer Control Register (offset 53h)
PCI-to-Memory write posting is enabled and dis-
abled via the PCI Read Write Buffer Control Regis-
ter (offset 54h) PCI master reads from main memory
always result in the PCMC and LBXs reading the
requested data and prefetching the next seven
Dwords
Seven Programmable Attribute Map (PAM) Regis-
ters (offsets 59h – 5Fh) are used to specify the
cacheability and read write status of the memory
space between 512 KBytes and 1 MByte Each PAM
Register defines a specific address area enabling
the system to selectively mark specific memory
ranges as cacheable read-only write-only read
write or disabled When a memory range is disabled
all CPU accesses to that range are directed to PCI
Two other registers also affect the DRAM interface
the Memory Space Gap Register (offsets 78h – 79h)
and the Frame Buffer Range Register (offsets 7Ch –
7Fh) The Memory Space Gap Register is used to
place a logical hole in the memory space between
1 MByte to 16 MBytes to accommodate memory
mapped ISA boards The Frame Buffer Range Reg-
ister is used to map a linear frame buffer into the
Memory Space Gap or above main memory When
enabled accesses to these ranges are never direct-
ed to the DRAM interface but are always directed to
PCI
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