82434LX Datasheet, PDF (121/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 82434NX DRAM Interface
This section describes the 82434NX DRAM inter-
face Changes in the 82430NX PCIset from the
82430 PCIset include
1 Increased maximum DRAM memory size to
512 MBytes The 82430NX PCIset increases the
maximum memory array size from 192 MBytes to
512 MBytes
2 Two additional row address lines (RAS 7 6 ) for
a total of eight (RAS 7 0 )
3 Addition of 50 MHz host-bus optimized DRAM
timing sets
4 Three additional registers are added to support
the increased memory sizeDRAM Row Boundary
Registers 6 and 7 (DRB 7 6 ) and the DRAM
Row Boundary Extension (DRBE) Register
5 Modified MA 11 0 timing to provide more
MA 11 0 setup time to CAS 7 0 assertion
6 2 1 DRAM ADDRESS TRANSLATION
The MA 11 0 lines are translated from the host ad-
dress lines A 26 3 for all memory accesses except
those targeted to memory that has been remapped
as a result of the creation of a memory space gap in
the lower extended memory area In the case of a
cycle targeting remapped memory the least signifi-
cant bits come directly from the host address while
the more significant bits depend on the memory
space gap start address gap size and the size of
main memory
Table 15 DRAM Address Translation
Memory Address 11 10 9
8
7
6
5
4
3
2
1
0
MA 11 0
Column Address A25 A23 A21 A11 A10 A9 A8 A7 A6 A5 A4 A3
Row Address
A26 A24 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12
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