82434LX Datasheet, PDF (17/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
2 1 Host Interface
Signal Type
Description
A 31 0
t s ADDRESS BUS A 31 0 are the address lines of the Host Bus A 31 3 are connected to
the CPU A 31 3 lines and to the LBXs A 2 0 are only connected to the LBXs Along with
the byte enable signals the A 31 3 lines define the physical area of memory or I O being
accessed During CPU cycles the A 31 3 lines are inputs to the PCMC They are used for
address decoding and second level cache tag lookup sequences Also during CPU cycles
A 2 0 are outputs and are generated from BE 7 0 A 27 24 provide hardware
strapping options for test features For more details on theses options refer to Section
11 0 Testability
During inquire cycles A 31 5 are inputs from the LBXs to the CPU and the PCMC to
snoop the first and the second level cache tags respectively In response to a Flush or
Flush Acknowledge Special Cycle the PCMC asserts AHOLD and drives the addresses of
the second level cache lines to be written back to main memory on A 18 7
During CPU to PCI configuration cycles the PCMC drives A 31 0 with the PCI
configuration space address that is internally derived from the CPU physical I O address
All PCMC internal configuration registers are accessed via A 31 0 During CPU reads
from PCMC internal configuration registers the PCMC asserts AHOLD and drives the
contents of the addressed register on A 31 0 The PCMC then signals the LBXs to copy
this value from the address lines onto the host data lines During writes to PCMC internal
configuration registers the PCMC asserts AHOLD and signals the LBXs to copy the write
data onto the A 31 0 lines
Finally when in deturbo mode the PCMC periodically asserts AHOLD and then drives
A 31 0 to valid logic levels to keep these lines from floating for an extended period of
time
A 31 28 provide hardware strapping options at powerup For more details on strapping
options refer to Section 8 0 System Clocking and Reset A 27 24 provide hardware
strapping options for test features For more details on these options refer to Section
11 0 Testability
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