82434LX Datasheet, PDF (126/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 3 4 Burst DRAM Write Page Hit
Figure 58 depicts a CPU burst write page hit to
DRAM The 82434NX decodes the CPU write cycle
as a DRAM page hit The HIG 4 0 lines are driven
to PCMWQ to post the write to the LBXs In the fig-
ure the write cycle is posted to the CPU-to-Memory
Posted Write Buffer at 3-1-1-1 When the cycle is
decoded as a page hit the PCMC asserts WE and
drives the RCMWQ command on MIG 2 0 to enable
the LBXs to drive the first Qword of the write onto
the memory data lines MEMDRV is then driven to
cause the LBXs to continue to drive the first Qword
for two more clocks CAS 7 0 are then negated
and asserted to perform the writes to the DRAMs as
the MA 1 0 lines advance through the Pentium
processor burst order A single write is similar to the
first write of the burst sequence The MIG 2 0 lines
are driven to NOPM in the clock when the last
CAS 7 0 are asserted
Figure 58 Burst DRAM Write Page Miss
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