82434LX Datasheet, PDF (83/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
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Figure 27 CPU Cache Read Miss Write-Back Line Fill with Standard SRAM (82434LX)
The CPU issues a memory read cycle that misses in
the second level cache In this instance a modified
line in the second level cache must be written back
to main memory before the new line can be filled
into the cache The PCMC inspects the valid and
modified bits for each of the lines within the ad-
dressed sector and writes back only the valid lines
within the sector that are in the modified state Dur-
ing the write-back cycle CA 4 3 begin with the ini-
tial value driven by the Pentium processor and pro-
ceed in the Pentium processor burst order CA 6 5
are used to count through the lines within the ad-
dressed sector When two or more lines must be
written back to main memory CA 6 5 count in the
direction from line 0 to line 3 CA 6 5 advance to
the next line to be written back to main memory
skipping lines that are not modified Figure 23 de-
picts the case of just one of the lines in a sector
being written back to main memory In this case the
entire line can be posted in the CPU-to-Main memo-
ry posted write buffer by driving the HIG 4 0 lines to
the PCMWQ command as each Qword is read from
the cache At the same time the required DRAM
read cycle is beginning As soon as the de-allocated
line is written into the posted write buffer the
HIG 4 0 lines are driven to CMR (CPU Memory
Read) to allow data to propagate from the DRAM
data lines to the CPU data lines The CWE 7 0
lines are not generated from a delayed version of
HCLK (as they are in the case of CPU to second
level cache burst write) but from ordinary HCLK ris-
ing edges CMR is driven on the HIG 4 0 lines
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