82434LX Datasheet, PDF (28/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
2 5 LBX Interface
Signal Type
Description
HIG 4 0
out HOST INTERFACE GROUP HIG 4 0 are outputs of the PCMC used to control the
LBX HA (Host Address) and HD (Host Data) buses Commands driven on HIG 4 0
cause the host data and or address lines to be either driven or latched by the LBXs
See the 82433LX (LBX) Local Bus Accelerator Data Sheet for a listing of the
HIG 4 0 commands
MIG 2 0
out MEMORY INTERFACE GROUP MIG 2 0 are outputs of the PCMC and control the
LBX MD (Memory Data) bus Commands driven on the MIG 2 0 lines cause the
memory data lines to be either driven or latched by the LBXs See the 82433LX (LBX)
Local Bus Accelerator Data Sheet for a listing of the MIG 2 0 commands
MDLE
out MEMORY DATA LATCH ENABLE During CPU reads from main memory MDLE is
used to control the latching of memory read data on the CPU data bus MDLE is
negated as CAS 7 0 are negated to close the latch between the memory data bus
and the host data bus During CPU reads from main memory the PCMC closes the
memory data to host data latch in the LBXs as BRDY is asserted and opens the
latch after the CPU has sampled the data
PIG 3 0
out PCI INTERFACE GROUP PIG 3 0 are outputs of the PCMC used to control the LBX
AD (PCI Address Data) bus Commands driven on the PIG 3 0 lines cause the AD
lines to be either driven or latched See the 82433LX (LBX) Local Bus Accelerator
Data Sheet for a listing of the PIG 3 0 commands
DRVPCI
out DRIVE PCI DRVPCI acts as an output enable for the LBX AD lines When sampled
asserted the LBXs begin driving the PCI AD lines When negated the AD lines on
the LBXs are tri-stated The LBX AD lines are tri-stated asynchronously from the
falling edge of DRVPCI
EOL
in END OF LINE EOL is asserted by the low order LBX when a PCI master read or
write transaction is about to overrun a cache line boundary EOL has an internal pull-
up resistor inside the PCMC The low order LBX EOL signal connects to this PCMC
input The high order LBX EOL signal is connected to ground through an external
pull-down resistor
PPOUT 1 0
in PCI PARITY OUT These signals reflect the parity of the 32 AD lines driven from or
latched in the LBXs depending on the command driven on PIG 3 0 The PPOUT0
pin has a weak internal pull-down resistor The PPOUT1 pin has a weak internal pull-
up resistor
2 6 Reset And Clock
Signal
Type
Description
HCLKOSC
in HOST CLOCK OSCILLATOR The HCLKOSC input is driven externally by a
crystal oscillator The PCMC generates six copies of HCLK from HCLKOSC
(HCLKA–HCLKF) During power-up HCLKOSC must stabilize for 1 ms before
PWROK is asserted If an external clock driver is used to clock the CPU PCMC
LBXs and second level cache SRAMs instead of the HCLKA – HCLKF outputs
HCLKOSC must be tied either high or low
HCLKA–HCLKF out HOST CLOCK OUTPUTS HCLKA – HCLKF are six low skew copies of the host
clock These outputs eliminate the need for an external low skew clock driver
28