82434LX Datasheet, PDF (45/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 12 HCS HOST CPU SELECTION REGISTER
Address Offset
Default Value
Access
Size
50h
82h (82434LX)
A2h (83434NX)
Read Write Read Only
8 bits
The HCS Register is used to specify the Host CPU type and speed This 8-bit register is also used to enable
and disable the first level cache
Bits Access
Description
75
RO HOST CPU TYPE (HCT) This field defines the Host CPU type
82434LX
These bits are hardwired to 100 which selects the Pentium processor All other
combinations are reserved
82434NX
In the 82434NX these bits are reserved Reads and writes to these bits have no effect
43
RESERVED
2
R W FIRST LEVEL CACHE ENABLE (FLCE) FLCE enables and disables the first level cache
When FLCE^e1 the PCMC responds to CPU cycles with KEN asserted for cacheable
memory cycles When FLCE^e0 KEN is always negated This prevents new cache line
fills to either the first level or second level caches
1 0 R W HOST OPERATING FREQUENCY (HOF) The DRAM refresh rate is adjusted according to
the frequency selected by this field For the 82434LX only bit 0 is used and bit 1 is
reserved
82434LX
Bit 1 is reserved If bit 0 is 1 the 82434LX supports a 66 MHz CPU If bit 0 is 0 the
82434LX supports a 60 MHz CPU
82434NX
These bits select the Host CPU frequency supported as follows
Bits 1 0 Host CPU Frequency
00 Reserved
01 50 MHz
10 60 MHz
11 66 MHz
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