82434LX Datasheet, PDF (105/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 1 DRAM CONFIGURATIONS
Figure 42 illustrates a 12-SIMM configuration which
supports single-sided SIMMs A row in the DRAM
array is made up of two SIMMs which share a com-
mon RAS line SIMM0 and SIMM1 are connected
to RAS0 and therefore comprise row 0 SIMM10
and SIMM11 form row 5 Within any given row the
two SIMMs must be the same size Among the six
rows SIMM densities can be mixed in any order
That is there are no restrictions on the ordering of
SIMM densities among the six rows
The low order LBX (LBXL) is connected to byte
lanes 5 4 1 and 0 of the host and memory data
buses and the lower two bytes of the PCI AD bus
The high order LBX (LBXH) is connected to byte
lanes 7 6 3 and 2 of the host and memory data
buses and the upper two bytes of the PCI AD bus
Thus SIMMs connected to LBXL are connected to
CAS 5 4 1 0 and SIMMs connected to LBXH are
connected to CAS 7 6 3 2
The MA 10 0 and WE lines are externally buff-
ered to drive the large capacitance of the memory
array Three buffered copies of the MA 10 0 and
WE signals are required to drive the six row array
Figure 43 illustrates a 6-SIMM configuration that
supports either single- or double-sided SIMMs In
this configuration single- and double-sided SIMMs
can be mixed For example if single-sided SIMMs
are installed into the sockets marked SIMM0 and
SIMM1 then RAS0 is connected to the SIMMs
and RAS1 is not connected Row 0 is then popu-
lated and row 1 is empty Two double-sided SIMMs
could then be installed in the sockets marked
SIMM2 and SIMM3 populating rows 2 and 3
6 1 2 DRAM ADDRESS TRANSLATION
The 82434LX multiplexed row column address to
the DRAM memory array is provided by the
MA 10 0 signals The MA 10 0 bits are derived
from the host address bus as defined by Table 12
MA 10 0 are translated from the host address
A 24 3 for all memory accesses except those tar-
geted to memory that has been remapped as a re-
sult of the creation of a memory space gap in the
lower extended memory area In the case of a cycle
targeting remapped memory the least significant
bits come directly from the host address while the
more significant bits depend on the memory space
gap start address gap size and the size of main
memory
Memory Address
MA 10 0
Row Address
Column Address
Table 12 DRAM Address Translation
10
9
8
7
6
5
4
3
2
1
0
A24 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12
A23 A21 A11 A10 A9 A8 A7 A6 A5 A4 A3
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