82434LX Datasheet, PDF (84/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
throughout the DRAM read portion of the cycle With
the fourth assertion of BRDY the HIG 4 0 lines
change to NOPC The LBXs however do not tri-
state the host data lines until MDLE rises
CWE 7 0 and MDLE track such that MDLE will
not rise before CWE 7 0 Thus the LBXs contin-
ue to drive the host data lines until CWE 7 0 are
negated CA 6 3 remain at the valid values until the
clock after the last BRDY providing address hold
time to CWE 7 0 rising
PEN is asserted as shown if the MCHK DRAM L2
Cache Data Parity Error bit in the Error Command
Register (offset 70h) is set If the second level cache
supports parity PEN is always asserted during
CPU read cycles in the third clock in case the cycle
hits in the cache
If more than one line must be written back to main
memory the PCMC fills the CPU-to-Main Memory
Posted Write Buffer and loads another Qword into
the buffer as each Qword write completes into main
memory The writes into DRAM proceed as page hit
write cycles from one line to the next completing at
a rate of X-4-4-4-5-4-4-4-5-4-4-4 for a three line
write-back All modified lines except for the last one
to be written back are posted and written to memory
before the DRAM read cycle begins The last line to
be written back is posted as the DRAM read cycle
begins Thus the read data is returned to the CPU
before the last line is retired to memory
The line which was written into the second level
cache is marked valid and unmodified by the PCMC
All the other lines in the sector are marked invalid A
subsequent CPU read cycle which hits in the same
sector (but a different line) in the second level cache
would then simply result in a line fill without any
write-back
5 1 3 BURST SRAM CACHE CYCLES (82434LX)
The following sections show the activity of the sec-
ond level cache interface when burst SRAMs are
used for the second level cache
5 1 3 1 Burst Read (82434LX)
Figure 28 depicts a burst read from the second level
cache with burst SRAMs
290479 – 30
Figure 28 CPU Burst Read from Second Level Cache with Burst SRAM (82434LX)
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