82434LX Datasheet, PDF (125/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 3 3 Burst DRAM Read Row Miss
Figure 57 depicts a CPU to DRAM burst read row
miss cycle The 82434NX decodes the CPU address
as a row miss and switches from initially driving the
column address to driving the row address on the
MA 11 0 lines The RAS signal that was asserted
is negated and the RAS for the currently accessed
row is asserted (RAS is asserted 1 clock earlier in
0-Active RAS Mode ) The PCMC then switches
the MA 11 0 lines to drive the column address and
asserts CAS 7 0 CMR (CPU Memory Read) is
driven on the HIG 4 0 lines to enable the memory
data to host data path through the LBXs The PCMC
advances the MA 1 0 lines through the microproc-
essor burst order negating and asserting
CAS 7 0 to read each Qword The MD 63 0 data
is sampled with HCLK in the LBXs when MDLE is
asserted and driven on the host bus the following
cycle to meet the setup time of the CPU BRDY is
then asserted When MDLE is negated the LBX
continues to drive the latched HD 63 0 to ensure
that the data hold time to CWE 7 0 is met for
standard SRAMs The LBXs tri-state the host data
bus when HIG 4 0 change to NOPC and MDLE ris-
es A single read row miss from DRAM is similar to
the first read of this sequence The HIG 4 0 lines
are driven to NOPC when the last BRDY is
asserted
Figure 57 Burst DRAM Read Cycle-Row Miss
290479 – 66
125