82434LX Datasheet, PDF (16/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
As a PCI device the PCMC contains all of the re-
quired PCI configuration registers The Host CPU
reads and writes these registers as described in
Section 3 0 Register Description
1 2 4 DRAM MEMORY OPERATIONS
The PCMC contains a DRAM controller that sup-
ports CPU and PCI master accesses to main memo-
ry The PCMC DRAM interface supplies the control
signals and address lines and the LBXs supply the
data path DRAM parity is generated for main mem-
ory writes and checked for memory reads
For the 82434LX the memory array is 64-bits wide
and ranges in size from 2 MBytes–192 MBytes The
array can be implemented with either single-sided or
double-sided SIMMs DRAM SIMM sizes of 256K x
36 1M x 36 and 4M x 36 are supported
For the 82434NX the memory array is 64-bits wide
and ranges in size from 2 MBytes–512 MBytes The
array can be implemented with either single-sided or
double-sided SIMMs DRAM SIMM sizes of 256K x
36 1M x 36 4M x 36 and 16M x 36 are supported
To provide optimum support for the various cache
configurations and the resultant mix of bus cycles
the system designer can select between 0-active
RAS and 1-active RAS modes These modes af-
fect the behavior of the RAS signal following either
CPU-to-main memory cycles or PCI-to-main memory
cycles
The PCMC also provides programmable memory
and cacheability attributes on 14 memory segments
of various sizes in the ISA compatibility range
(512 KByte–1 MByte address range) Access rights
to these memory segments from the PCI Bus are
controlled by the expansion bus bridge
The PCMC permits a gap to be created in main
memory within the 1 MByte–16 MBytes address
range accommodating ISA devices which are
mapped into this range (e g ISA LAN card or an ISA
frame buffer)
1 2 5 3 3V SIGNALS
The 82434NX PCMC drives 3 3V signal levels on the
CPU and second level cache interfaces Thus no
extra logic (i e 5V 3 3V translation) is required when
interfacing to 3 3V processors and SRAMs Six of
the power pins on the 82434NX are VDD3 pins
These pins are connected to a 3 3V power supply
The VDD3 pins power the output buffers on the CPU
and second level cache interfaces The VDD3 pins
also power the output buffers for the HCLK A-F
outputs
2 0 SIGNAL DESCRIPTIONS
This section provides a detailed description of each
signal The signals are arranged in functional groups
according to their associated interface The states of
all of the signals during hard reset are provided in
Section 8 0 System Clocking and Reset
The ‘‘ ’’ symbol at the end of a signal name indi-
cates that the active or asserted state occurs when
the signal is at a low voltage level When ‘‘ ’’ is not
present after the signal name the signal is asserted
when at the high voltage level
The terms assertion and negation are used exten-
sively This is done to avoid confusion when working
with a mixture of ‘‘active-low’’ and ‘‘active-high’’ sig-
nals The term assert or assertion indicates that a
signal is active independent of whether that level is
represented by a high or low voltage The term ne-
gate or negation indicates that a signal is inactive
The following notations are used to describe the sig-
nal type
in Input is a standard input-only signal
out Totem pole output is a standard active driver
o d Open drain
t s Tri-State is a bi-directional tri-state input out-
put pin
s t s Sustained tri-state is an active low tri-state sig-
nal owned and driven by one and only one
agent at a time The agent that drives a s t s
pin low must drive it high for at least one clock
before letting it float A new agent can not
start driving a s t s signal any sooner than
one clock after the previous owner tri-states it
An external pull-up is required to sustain the
inactive state until another agent drives it and
must be provided by the central resource
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