82434LX Datasheet, PDF (31/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
The following nomenclature is used for access attributes
RO Read Only If a register is read only writes to this register have no effect
R W Read Write A register with this attribute can be read and written
R WC Read Write Clear A register bit with this attribute can be read and written However a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect
3 1 I O Mapped Registers
The 82434LX PCMC contains three registers that reside in the CPU I O address space the Configuration
Space Enable (CSE) Register the Turbo-Reset Control (TRC) Register and the Forward (FORW) Register
These registers can not reside in PCI configuration space because of the special functions they perform The
CSE Register enables disables the configuration space and hence can not reside in that space The TRC
Register enables disables deturbo mode which effectively slows the processor to accommodate software
programs that rely on the slow speed of PC XT systems to time certain events The FORW Register deter-
mines which of the possible hierarchical PCI Buses a cycle is directed The 82434LX uses mechanism 2 for
accessing PCI configuration space
The 82434NX PCMC contains five registers that reside in the CPU I O address spacethe Configuration Ad-
dress (CONFADD) Register the Configuration Space Enable (CSE) Register the Turbo-Reset Control (TRC)
Register the Forward (FORW) Register and the PCI Mechanism Control (PMC) Register The CSE TRC and
FORW Registers are the same for both the 82434LX and 82434NX PCMCs The 82434NX can use either
Configuration Access Mechanism 1 or 2 for accessing PCI configuration space When Configuration Ac-
cess Mechanism 1 is used (See Section 3 2 PCI Configuration Space Mapped Registers) The CONFADD
Register enables disables the configuration space and determines what portion of configuration space is
visible through the Configuration Data (CONFDATA) window The CSE and FORW Registers are used for
Configuration Access Mechanism 2 The PCI Mechanism Control (PMC) Register selects whether Configura-
tion Access Mechanism 1 or 2 is used (see the Rev 2 0 PCI Local Bus Specification)
3 1 1 CONFADD CONFIGURATION ADDRESS REGISTER
I O Address
Default Value
Access
Size
0CF8h Accessed as a Dword
00000000h
Read Write
32 bits
CONFADD is a 32-bit register used in Configuration Access Mechanism 1 It is accessed only when refer-
enced as a Dword and PCAMS in the PMC Register is set to 1 Byte or Word references ‘‘pass through’’ the
CONFADD Register to the I O locations ‘‘behind’’ it For example a byte access to 0CF8h will access the CSE
Register while a word access to CF8h will access both the CSE and TRC Registers The CONFADD Register
contains the Bus Number Device Number Function Number and Register Number where the CONFDATA
window is located
31