82434LX Datasheet, PDF (80/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
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Figure 24 Burst Read Followed by Pipelined Write with Standard SRAM (82434LX)
5 1 2 3 Cache Line Fill (82434LX)
If the CPU issues a memory read cycle to cacheable
memory that is not in the second level cache a first
and second level cache line fill occurs Figure 25
depicts a CPU read cycle that results in a line fill into
the first and second level caches
Figure 27 depicts the host bus activity during a CPU
read cycle that forces a write-back from the second
level cache to the CPU-to-memory posted write buff-
er as the DRAM read cycle begins
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