82434LX Datasheet, PDF (86/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
5 1 3 2 Burst Write (82434LX)
A burst write cycle is used to write back a line from
the first level cache to either the second level cache
or DRAM A burst write cycle from the first level
cache to the second level cache is shown in Fig-
ure 30
The Pentium processor always writes back lines
starting with the low order Qword advancing to the
high order Qword CADS is asserted in the second
clock CWE 7 0 and BRDY are asserted in the
third clock CADV assertion is delayed by one
clock relative to the burst read cycle HIG 4 0 are
driven to PCMWQ (Post CPU-to-Memory Write Buff-
er Qword) only when the PCMC is programmed for a
write-through write policy When programmed for
write-back mode the modified bit associated with
the line is set within the PCMC The single write is
very similar to the first write in a burst write CADS
is asserted in the second clock BRDY and
CWE 7 0 are asserted in the third clock A burst
read cycle followed by a pipelined single write cycle
is depicted in Figure 31
290479 – 32
Figure 30 Burst Write to Second Level Cache with Burst SRAM (82434LX)
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