82434LX Datasheet, PDF (29/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
HCLKIN
CPURST
Type
Description
in HOST CLOCK INPUT All timing on the host DRAM and second level cache interfaces
is based on HCLKIN If an external clock driver is used to clock the CPU PCMC LBXs
and second level cache SRAMs the externally generated clock must be connected to
HCLKIN During power-up HCLKIN must stabilize for 1 ms before PWROK is asserted
out CPU HARD RESET The CPURST pin is asserted in response to one of two conditions
Powerup
82434LX During powerup the 82434LX asserts CPURST when PWROK is negated
When PWROK is asserted the 82434LX first ensures that it has been initialized before
negating CPURST
82434NX During powerup the 82434NX PCMC negates CPURST while PWROK is
negated When PWROK is asserted the 82434NX asserts CPURST for 2 ms
Software
CPURST is also asserted when the System Hard Reset Enable bit in the Turbo-Reset
Control Register (I O address 0CF9h) is set to 1 and the Reset CPU bit toggles from 0
to 1 (82434LX and 82434NX) CPURST is driven synchronously to the rising edge of
HCLKIN
INIT
out INITIALIZATION INIT is asserted in response to any one of two conditions When the
System Hard Reset Enable bit in the Turbo-Reset Control Register is reset to 0 and the
Reset CPU bit toggles from 0 to 1 the PCMC initiates a soft reset by asserting INIT
The PCMC also initiates a soft reset by asserting INIT in response to a shutdown
special cycle In both cases INIT is asserted for a minimum of 2 Host clocks
PWROK
in POWER OK When asserted PWROK is an indication to the PCMC that power and
HCLKIN have stabilized for at least 1 ms PWROK can be driven asynchronously
82434LX When PWROK is negated the 82434LX asserts both CPURST and
PCIRST When PWROK is driven high the 82434LX ensures that it is initialized
before negating CPURST and PCIRST
82434NX When PWROK is negated the 82434NX negates CPURST and asserts
PCIRST When PWROK is asserted the 82434NX asserts CPURST for 2 ms
PCIRST is negated 1 ms after PWROK is asserted
PCLKOUT out PCI CLOCK OUTPUT PCLKOUT is internally generated by a Phase Locked Loop
(PLL) that divides the frequency of HCLKIN by 2 This output must be buffered
externally to generate multiple copies of the PCI Clock One of the copies must be
connected to the PCLKIN pin
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