82434LX Datasheet, PDF (64/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
4 0 PCMC ADDRESS MAP
The Pentium processor has two distinct physical ad-
dress spaces Memory and I O The memory ad-
dress space is 4 GBytes and the I O address space
is 64 KBytes The PCMC maps accesses to these
address spaces as described in this section
4 1 CPU Memory Address Map
Figure 9 shows the address map for the 4 GByte
Host CPU memory address space Depending on
the address range and whether a memory gap is
enabled via the MSG Register the PCMC forwards
CPU memory accesses to either main memory or
PCI memory Accesses forwarded to main memory
invoke operations on the DRAM interface and ac-
cesses forwarded to PCI memory invoke operations
on PCI Mapping to the PCI Bus permits PCI or
EISA ISA Bus-based memory
The main memory size ranges from 2 MBytes –
192 MBytes for the 82434LX and 2 MBytes –
512 MBytes for the 82434NX Memory accesses
above 192 MBytes (512 MBytes for the 82434NX)
are always forwarded to PCI In addition a memory
gap can be created in the 1 MByte–16 MBytes
region that provides a window to PCI-based memo-
ry The location and size of the gap is programma-
ble Accesses to addresses in the gap are ignored
by the DRAM controller and forwarded to PCI Note
that CPU memory accesses that are forwarded to
PCI (including the Memory Space Gap) are not
cacheable Only main memory controlled by the
PCMC DRAM interface is cacheable
4 2 System Management RAM
SMRAM
The PCMC supports the use of main memory as
System Management RAM (SMRAM) enabling the
use of System Management Mode This function is
enabled and disabled via the DRAM Control Regis-
ter When this function is disabled the PCMC mem-
ory map is defined by the DRB and PAM Registers
When SMRAM is enabled the PCMC reserves the
top 64-KBytes of main memory for use as SMRAM
SMRAM can also be placed at A0000 – AFFFFh or
B0000 – BFFFFh via the SMRAM Space Register
Enhanced SMRAM features can also be enabled via
this register PCI masters can not access SMRAM
when it is programmed to the A or B segments
Figure 9 CPU Memory Address Map Full Range
290479 – 11
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