82434LX Datasheet, PDF (119/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 5 2 CAS -before-RAS Refresh-Single
Figure 53 depicts a CAS -before-RAS refresh cy-
cle when the 82434LX is programmed for single re-
fresh cycles The diagram shows a CPU read cycle
completing as the refresh timing inside the PCMC
generates a refresh request The CPU read cycle is
less than a Qword therefore a hidden refresh is not
initiated After the CPU read cycle completes all of
the RAS and CAS lines are negated The PCMC
then asserts CAS 7 0 and then sequentially as-
serts the RAS lines starting with RAS1 since
RAS0 was the last RAS line asserted Each
RAS line is asserted for six clocks
Figure 53 CAS -before-RAS Refresh-Single
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