82434LX Datasheet, PDF (122/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 2 CYCLE TIMING SUMMARY
The 82434NX PCMC DRAM performance for
50 MHz Host bus clock is summarized in Table 13
for all CPU read and write cycles The 60 66 MHz
MA 11 0 timings when in X-4-4-4 mode have one
difference from the 82434LX MA 11 0 timings The
MA lines switch to the next address in the burst se-
quence one clock sooner than in the 82434LX pro-
viding more MA 11 0 setup time to CAS 7 0 as-
sertion The 60 66 MHz DRAM timings for write cy-
cles have been improved by 1 clock for all leadoffs
The 50 MHz timings shown below are selected by
HOF^e00 DBT^e11 RWS^e0 and CWS^e0
Table 16 CPU to DRAM Performance Summary
for 50 MHz Host Bus Clock
Cycle Type
x-3-3-3 Timing⁽¹⁾
Read (Page Hit Row Miss
Page Miss)
6 10 12-3-3-3
Posted Write
4-1-1-1
Write (Page Hit Row Miss
Page Miss)
10 11 13-3-3-3
0-Active RAS
Mode Reads
9-3-3-3
0-Active RAS
Mode Writes
9-3-3-3
NOTES
1 Single cycle timings are identical to these leadoff
timings
Table 17 Refresh Cycle Performance
(Independent of CPU frequency)
Refresh
Type
Hidden
Refresh
RAS Only
Refresh
CAS -
Before-
RAS
Single
16
17
18
Burst of Four 64
68
72
6 2 3 CPU TO DRAM BUS CYCLES
In this section all timing diagrams are for 50 MHz
DRAM timing 1-Active RAS mode The 60 66 MHz
MA 11 0 timings when in X-4-4-4 mode have one
difference from the 82434LX MA 11 0 timings The
MA lines switch to the next address in the burst se-
quence one clock sooner than in the 82434LX The
write cycle leadoffs are 1 clock earlier for 82430NX
than 82430 (the MIGs and CAS timings improved by
1 clock) The 0-Active RAS modes closely resem-
ble the row miss cases In 0-Active RAS mode
RAS is asserted one clock sooner than is shown in
the row miss timing diagrams
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