82434LX Datasheet, PDF (136/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
7 3 3 CPU WRITE TO PCI DEVICE
CONFIGURATION REGISTER
In order to write to or read from a PCI device config-
uration register the Key field in the CSE register
must be programmed to a non-zero value enabling
configuration space When configuration space is
enabled PCI device configuration registers are ac-
cessed by CPU I O accesses within the range of
CnXXh where each PCI device has a unique non-
zero value of n This allows a separate configuration
space for each of 15 devices on PCI Recall that
when configuration space is enabled the PCMC
configuration registers are mapped into I O ports
C000h through C0FFh
A write to a PCI device configuration register is
shown in Figure 67 The PCMC internally latches the
host address lines and byte enables The PCMC as-
serts AHOLD to tri-state the CPU address bus and
drives the address lines with the translated address
for the PCI configuration cycle The translation is de-
scribed in Section 3 2 PCI Configuration Space
Mapped Registers On the HIG 4 0 lines the PCMC
signals the LBXs to latch either the upper Dword of
the host data bus or the lower Dword of the host
data bus to be driven onto PCI during the data phase
of the PCI cycle On the PIG 3 0 lines the PCMC
signals the LBXs to drive the latched host address
lines on the PCI AD 31 0 lines The upper two bytes
of the address lines are used during configuration as
IDSEL signals for the PCI devices The IDSEL pin on
each PCI device is connected to one of the
AD 31 17 lines
The PCMC drives the command for a configuration
write (1011) onto the C BE 3 0 lines and asserts
FRAME for one PCI clock The PCMC drives the
PIG 3 0 lines signaling the LBXs to drive the con-
tents of the PCI write buffer onto the PCI AD 31 0
lines This command is driven for only one PCI clock
before returning to the SCPA command on the
PIG 3 0 lines The LBXs continue to drive the
AD 31 0 lines with the valid write data as long as
DRVPCI is asserted The PCMC then asserts
IRDY and waits until sampling the TRDY signal
active When TRDY is sampled asserted the
PCMC negates DRVPCI tri-stating the LBX AD 31 0
lines BRDY is asserted for one clock to terminate
the CPU cycle
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