82434LX Datasheet, PDF (120/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 1 5 3 Hidden Refresh-Single
Figure 54 depicts a hidden refresh cycle which takes
place after a DRAM read page hit cycle The dia-
gram shows a CPU read cycle completing as the
refresh timing inside the 82434LX generates a re-
fresh request The CPU read cycle is an entire
Qword therefore a hidden refresh is initiated After
the CPU read cycle completes RAS is negated
but all eight CAS lines remain asserted The
PCMC then sequentially asserts the RAS lines
starting with RAS1 since RAS0 was the last ac-
tive RAS line Each RAS line is asserted for six
clocks
Figure 54 Hidden Refresh-Single
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