82434LX Datasheet, PDF (138/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
7 3 4 CPU READ FROM PCI DEVICE
CONFIGURATION REGISTER
In order to write to or read from a PCI device config-
uration register the Key field in the CSE register
must be programmed to a non-zero value enabling
configuration space When configuration space is
enabled PCI device configuration registers are ac-
cessed by CPU I O accesses within the range of
CnXXh where each PCI device has a unique non-
zero value of n This allows a separate configuration
space for each of 15 devices on PCI Recall that
when configuration space is enabled the PCMC
configuration registers occupy I O addresses
C0XXH
A CPU read from a PCI device configuration register
is shown in Figure 68 The PCMC internally latches
the host address lines and byte enables The PCMC
asserts AHOLD to tri-state the CPU address bus
The PCMC drives the address lines with the translat-
ed address for the PCI configuration cycle The
translation is described in Section 3 2 PCI Configu-
ration Space Mapped Registers On the PIG 3 0
lines the PCMC signals the LBXs to drive the
latched host address lines on the PCI AD 31 0
lines The upper two bytes of the address lines are
used during configuration as IDSEL signals for the
PCI devices The IDSEL pin on each PCI device is
connected to one of the AD 31 17 lines
The PCMC drives the command for a configuration
read (1010) onto the C BE 3 0 lines and asserts
FRAME for one PCI clock The PCMC drives the
PIG 3 0 lines signaling the LBXs to latch the data
on the PCI AD 31 0 lines into the CPU-to-PCI first
read prefetch buffer The PCMC then drives the
HIG 4 0 lines signaling the LBXs to drive the data
from the buffer onto the host data lines The PCMC
asserts IRDY and waits until sampling TRDY ac-
tive After TRDY is sampled active BRDY is as-
serted for one clock to terminate the CPU cycle
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