82434LX Datasheet, PDF (67/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
For the 82434NX six PCMC registers are located in
the CPU I O address space the Configuration
Space Enable (CSE) Register the Configuration Ad-
dress Register (CONFADD) the Turbo-Reset Con-
trol (TRC) Register the Forward (FORW) Register
the PCI Mechanism Control (PMC) Register and the
Configuration Data (CONFDATA) Register
Except for the I O locations of the above mentioned
registers all other CPU I O accesses are mapped to
either PCI I O space or PCI configuration space If
the access is to PCI I O space the PCI address is
the same as the CPU address If the access is to PCI
configuration space the CPU address is mapped to
a configuration space address as described in Sec-
tion 3 0 Register Description
If configuration space is enabled via the CSE Regis-
ter (access mechanism 2) the PCMC maps ac-
cesses in the address range of C100h to CFFFh to
PCI configuration space Accesses to the PCMC
configuration register range (C000h to C0FFh) are
intercepted by the PCMC and not forwarded to PCI
If the configuration space is disabled in the CSE
Register CPU accesses to the configuration ad-
dress range (C000h to CFFFh) are forwarded to PCI
I O space
5 0 SECOND LEVEL CACHE
INTERFACE
This section describes the second level cache inter-
face for the 82434LX Cache (Section 5 1) and the
82434NX Cache (Section 5 2) The differences are
in the following areas
1 The 82434LX supports both write-through and
write-back cache policies The 82434NX only
supports the write-back policy
2 The 82434LX timings are for 60 and 66 MHz and
the 82434NX timings are for 50 60 and 66 MHz
Note that the cycle latencies for 60 and 66 MHz
are the same for both devices
3 When burst SRAMs are used to implement the
secondary cache address latches are not need-
ed for the 82434NX type SRAM connectivity
However a control bit has been added to the
82434NX that permits address latches for
82434LX type SRAM connectivity
4 A low-power second level cache standby mode
has been added to the 82434NX
5 There are new or changed cache control bits as
indicated by the shading in Section 3 0 Register
Description For example the 82434NX supports
zero wait-state cache at 50 MHz via the zero
wait-state control bit
NOTE
 Second level cache sizes and organization
are the same for the 82434LX and
82434NX
 The general operation of the second level
cache write-back policy is the same for the
82434LX and 82434NX For example the
Valid and Modified bits operate the same
for both devices In addition snoop opera-
tions are the same for both devices as
well as the handling of flush flush ac-
knowledge and write-back special cycles
5 1 82434LX Cache
The 82434LX PCMC integrates a high performance
write-back write-through second level cache con-
troller providing integrated tags and a full first level
and second level cache coherency mechanism The
second level cache controller can be configured to
support either a 256-KByte cache or a 512 KByte
cache using either synchronous burst SRAMs or
standard asynchronous SRAMs The cache is direct
mapped and can be configured to support either a
write-back or write-through write policy Parity on the
second level cache data SRAMs is optional
The 82434LX contains 4096 address tags Each tag
represents a sector in the second level cache If the
second level cache is 256-KByte each tag repre-
sents two cache lines If the second level cache is
512-KByte each tag represents four cache lines
Thus in the 256-KByte configuration each sector
contains two lines In the 512-KByte configuration
each sector contains four lines Valid and modified
status bits are kept on a per line basis Thus in the
case of a 256-KByte cache each tag has two valid
bits and two modified bits associated with it In the
case of a 512-KByte cache each tag has four valid
and four modified bits associated with it Upon a
CPU read cache miss the PCMC inspects the valid
and modified bits within the addressed sector and
writes back to main memory only the lines marked
both valid and modified All of the lines in the sector
are then invalidated The line fill will then occur and
the valid bit associated with the allocated line will be
set Only the requested line will be fetched from
main memory and written into the cache If no write-
back is required all of the lines in the sector are
marked invalid The line fill then occurs and the valid
bit associated with the allocated line will be set
Lines are not allocated on write misses When a
CPU write hits a line in the second level cache the
modified bit for the line is set
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