82434LX Datasheet, PDF (13/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
ISA Bus
Figure 1 represents a system using the ISA Bus as
the second level I O bus It allows personal comput-
er platforms built around the PCI as a primary I O
bus to leverage the large ISA product base The ISA
Bus has 24-bit addressing and a 16-bit data path
EISA Bus
Figure 2 represents a system using the EISA Bus as
the second level I O bus It allows personal comput-
er platforms built around the PCI as a primary I O
bus to leverage the large EISA ISA product base
Combinations of PCI and EISA buses both of which
can be used to provide expansion functions will sat-
isfy even the most demanding applications
Along with compatibility for 16-bit and 8-bit ISA hard-
ware and software the EISA bus provides the fol-
lowing key features
 32-bit addressing and 32-bit data path
 33 MByte sec bus bandwidth
 Multiple bus master support through efficient arbi-
tration
 Support for autoconfiguration
1 1 2 BUS BRIDGES
Host PCI Bridge Chip Set (PCMC and LBX)
The PCMC and LBX enhance the system perform-
ance by allowing for concurrency between the Host
CPU Bus and PCI Bus giving each greater bus
throughput and decreased bus latency The LBX
contains posted write buffers for Host-to-PCI Host-
to-main memory and PCI-to-main memory transfers
The LBX also contains read prefetch buffers for
Host reads of PCI and PCI reads of main memory
There are two LBXs per system The LBXs are con-
trolled by commands from the PCMC The PCMC
LBX Host PCI bridge chip set is covered in more
detail in Section 1 2 PCMC Overview
PCI-EISA Bridge Chip Set (PCEB and ESC)
The PCEB provides the master slave functions on
both the PCI Bus and the EISA Bus Functioning as
a bridge between the PCI and EISA buses the
PCEB provides the address and data paths bus
controls and bus protocol translation for PCI-to-
EISA and EISA-to-PCI transfers Extensive data buff-
ering in both directions increase system perform-
ance by maximizing PCI and EISA Bus efficiency and
allowing concurrency on the two buses The PCEB’s
buffer management mechanism ensures data coher-
ency The PCEB integrates central bus control func-
tions including a programmable bus arbiter for the
PCI Bus and EISA data swap buffers for the EISA
Bus Integrated system functions include PCI parity
generation system error reporting and programma-
ble PCI and EISA memory and I O address space
mapping and decoding The PCEB also contains a
BIOS Timer that can be used to implement timing
loops The PCEB is intended to be used with the
ESC to provide an EISA I O subsystem interface
The ESC integrates the common I O functions
found in today’s EISA-based PCs The ESC incorpo-
rates the logic for EISA Bus controller enhanced
seven channel DMA controller with scatter-gather
support EISA arbitration 14 level interrupt control-
ler Advanced Programmable Interrupt Controller
(APIC) five programmable timer counters non-
maskable-interrupt (NMI) control and power man-
agement The ESC also integrates support logic to
decode peripheral devices (e g the flash BIOS real
time clock keyboard mouse controller floppy con-
troller two serial ports one parallel port and IDE
hard disk drive)
PCI ISA Bridge (SIO)
The SIO component provides the bridge between
the PCI Bus and the ISA Bus The SIO also inte-
grates many of the common I O functions found in
today’s ISA-based PCs The SIO incorporates the
logic for a PCI interface (master and slave) ISA in-
terface (master and slave) enhanced seven channel
DMA controller that supports fast DMA transfers and
scatter-gather data buffers to isolate the PCI Bus
from the ISA Bus and to enhance performance PCI
and ISA arbitration 14 level interrupt controller a
16-bit BIOS timer three programmable timer coun-
ters and non-maskable-interrupt (NMI) control logic
The SIO also provides decode for peripheral devices
(e g the flash BIOS real time clock keyboard
mouse controller floppy controller two serial ports
one parallel port and IDE hard disk drive)
1 2 PCMC Overview
The PCMC (along with the LBX) provides three basic
functions a cache controller a main memory DRAM
controller and a Host PCI bridge This section pro-
vides an overview of these functions Note that in
this document operational descriptions assume that
the PCMC and LBX components are used together
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