82434LX Datasheet, PDF (30/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
PCLKIN
PCIRST
TESTEN
Type
Description
in PCI CLOCK INPUT An internal PLL locks PCLKIN in phase with HCLKIN All timing on
the PCMC PCI interface is referenced to the PCLKIN input All output signals on the PCI
interface are driven from PCLKIN rising edges and all input signals on the PCI interface
are sampled on PCLKIN rising edges
out PCI RESET PCIRST is asserted to initiate hard reset on PCI PCIRST is asserted in
response to one of two conditions
Power-up
During power-up the PCMC asserts PCIRST when PWROK is negated
82434LX When PWROK is asserted the PCMC will first ensure that it has been
initialized before negating PCIRST
82434NX When PWROK is negated the 82434NX asserts PCIRST The 82434NX
then negates PCIRST 1 ms after PWROK is asserted
Software
PCIRST is also asserted when the System Hard Reset Enable bit in the Turbo Reset
Control Register is set to 1 and the Reset CPU bit toggles from 0 to 1 (82434LX and
82434NX) PCIRST is driven asynchronously
in TEST ENABLE TESTEN must be tied low for normal system operation
3 0 REGISTER DESCRIPTION
The 82434LX 82434NX PCMC contains two sets of software accessible registers These registers are ac-
cessed via the Host CPU I O address space The PCMC also contains a set of configuration registers that
reside in PCI configuration space and are used to specify PCI configuration DRAM configuration cache
configuration operating parameters and optional system features (see Section 3 2 PCI Configuration Space
Mapped Registers) The PCMC internal registers (both I O Mapped and Configuration registers) are only
accessible by the Host CPU and cannot be accessed by PCI masters The registers can be accessed as Byte
Word (16-bit) or Dword (32-bit) quantities All multi-byte numeric fields use ‘‘little-endian’’ ordering (i e lower
addresses contain the least significant parts of the field)
Some of the PCMC registers described in this section contain reserved bits These bits are labeled ‘‘R’’
Software must deal correctly with fields that are reserved On reads software must use appropriate masks to
extract the defined bits and not rely on reserved bits being any particular value On writes software must
ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions
must first be read merged with the new values for other bit positions and then written back
In addition to reserved bits within a register the PCMC contains address locations in the PCI configuration
space that are marked ‘‘Reserved’’ (Table 1) The PCMC responds to accesses to these address locations by
completing the Host cycle When a reserved register location is read 0000h is returned Writes to reserved
registers have no affect on the PCMC
Upon receiving a hard reset via the PWROK signal the PCMC sets its internal configuration registers to
predetermined default states The default state represents the minimum functionality feature set required to
successfully bring up the system Hence it does not represent the optimal system configuration It is the
responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configura-
tions cache configuration operating parameters and optional system features that are applicable and to
program the PCMC registers accordingly
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