82434LX Datasheet, PDF (24/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
COE 1 0
CWE 7 0
CBS 7 0
Type
Description
out CACHE OUTPUT ENABLE COE 1 0 are asserted when data is to be read from
the second level cache and are negated at all other times Two copies of this signal
are provided for timing reasons only The two copies are always driven to the same
logic level
out This signal pin has two functions depending on the type of SRAMs used for the
second level cache
CACHE WRITE ENABLES CWE 7 0 are asserted to write data to the second
level cache SRAMs on a byte-by-byte basis CWE7 controls the most significant
byte while CWE0 controls the least significant byte These signals are cache write
enables when using burst SRAMs (SRAM Type bit in SCC Register is 1) or when
using asynchronous SRAMs (SRAM Type bit in SCC Register is 0) and the Cache
Byte Control Bit is 1
CACHE BYTE SELECTS The CBS 7 0 lines provide byte control to the
secondary cache when using dual-byte select asynchronous SRAMs These signals
are Cache Byte select lines when the SRAM Type and Cache Byte Control Bits in the
SCC Register are both 0
2 4 PCI Interface
Signal Type
Description
C BE 3 0
t s PCI BUS COMMAND AND BYTE ENABLES C BE 3 0 are driven by the current
bus master during the address phase of a PCI cycle to define the PCI command and
during the data phase as the PCI byte enables The PCI commands indicate the
current cycle type and the PCI byte enables indicate which byte lanes carry
meaningful data C BE 3 0 are outputs of the PCMC during CPU cycles that are
directed to PCI C BE 3 0 are inputs when the PCMC acts as a slave The
command encodings and types are listed below
C BE 3 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Command
Interrupt Acknowledge
Special Cycle
I O Read
I O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Reserved
Memory Read Line
Memory Write and Invalidate
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