82434LX Datasheet, PDF (128/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
6 2 3 6 Burst DRAM Write Row Miss
Figure 60 depicts a CPU burst write row miss to
DRAM The 82434NX decodes the CPU write cycle
as a DRAM row miss and the HIG 4 0 lines are driv-
en to PCMWQ to post the write data into LBXs
When the cycle is decoded as a row miss the PCMC
negates the already active RAS signal switches
the MA 11 0 lines from the column address to the
row address and asserts the RAS signal for the
currently decoded row The PCMC asserts WE
and drives the RCMWQ command on MIG 2 0 to
enable the LBXs to drive the first Qword of the write
onto the memory data lines MEMDRV is then driven
to cause the LBXs to continue to drive the first
Qword The PCMC then switches the MA 11 0 lines
to the column address and asserts CAS 7 0 to
initiate the first write CAS 7 0 are then negated
and asserted to perform the writes to the DRAMs as
the MA 1 0 lines advance through the microproces-
sor burst order A single write is similar to the first
write of the burst sequence The MIG 2 0 lines are
driven to NOPM in the clock when the last
CAS 7 0 are asserted
Figure 60 Burst DRAM Write Cycle-Row Miss
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