82434LX Datasheet, PDF (90/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
of the lines in a sector being written back to main
memory In this case the entire line can be posted in
the CPU-to-Memory Posted Write Buffer by driving
the HIG 4 0 lines to PCMWQ as each Qword is
read from the cache At the same time the required
DRAM read cycle is beginning After the de-allocat-
ed line is written into the posted write buffer the
HIG 4 0 lines are driven to CMR (CPU Memory
Read) to allow data to propagate from the DRAM
data lines to the CPU data lines Figure 29 assumes
that the read from DRAM is a page hit and thus the
first Qword is already read from the DRAMs when
the transfer from cache to the CPU to Memory post-
ing buffer is complete The rest of the DRAM cycle
completes at a -4-4-4 rate CADV is asserted with
the last three BRDY assertions CMR is driven on
the HIG 4 0 lines throughout the DRAM read por-
tion of the cycle Upon the fourth assertion of
BRDY the HIG 4 0 lines change to NOPC
PEN is asserted as shown if the MCHK DRAM L2
Cache Data Parity Error bit in the Error Command
Register (offset 70h) is set If the second level cache
supports parity PEN is always asserted during
CPU read cycles in clock 3 in case the cycle hits in
the cache
If more than one line must be written back to main
memory the PCMC fills the CPU-to-Main Memory
Posted Write Buffer and loads another Qword into
the buffer as each Qword write completes into main
memory The writes into DRAM proceed as page hit
write cycles from one line to the next completing at
a rate of X-4-4-4-5-4-4-4-5-4-4-4 for a three line
write-back when programmed for X-4-4-4 DRAM
write timing or X-3-3-3-4-3-3-3-4-3-3-3 when pro-
grammed for X-3-3-3 DRAM write timing All modi-
fied lines except for the last one to be written back
to memory are posted and retired to memory before
the DRAM read cycle begins The last line to be writ-
ten back is posted as the DRAM read cycle begins
Thus the read data is returned to the CPU before
the last line is retired to memory
The line which was written into the second level
cache is marked valid and unmodified by the PCMC
All the other lines in the block are marked invalid A
subsequent CPU read cycle which hits the same
sector (but a different line) in the second level cache
results in a line fill without any write-back
5 1 4 SNOOP CYCLES
Snoop cycles are the same for the 82434LX and
82434NX The inquire cycle is used to probe the first
level and second level caches when a PCI master
attempts to access main memory This is done to
maintain coherency between the first and second
level caches and main memory When a PCI master
first attempts to access main memory a snoop re-
quest is generated inside the PCMC The PCMC
supports up to two outstanding cycles on the CPU
address bus at a time Outstanding cycles include
both CPU initiated cycles and snoop cycles Thus if
the Pentium processor pipelines a second cycle
onto the host address bus the PCMC will not issue a
snoop cycle until the first CPU cycle terminates If
the PCMC were to initiate a snoop cycle before the
first CPU cycle were complete then for a brief period
of time three cycles would be outstanding Thus a
snoop request is serviced with a snoop cycle only
when either no cycle is outstanding on the CPU bus
or one cycle is outstanding
Snoop cycles are performed by driving the PCI mas-
ter address onto the CPU address bus and asserting
EADS The Pentium processor then performs a
tag lookup to determine if the addressed memory is
in the first level cache At the same time the PCMC
performs an internal tag lookup to determine if the
addressed memory is in the second level cache Ta-
ble 7 describes how a PCI master read from main
memory is serviced by the PCMC
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