82434LX Datasheet, PDF (61/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 24 SMRS SMRAM SPACE REGISTER
Address Offset
Default Value
Attribute
Size
72h
00h
Read Write
8 bits
The PCMC supports a 64-KByte SMRAM space that can be selected to reside at the top of main memory
segment A0000–AFFFFh or segment B0000–BFFFFh The SMM space defined by this register is not cache-
able This register defines a mechanism that allows the CPU to execute code out of the SMM space at either
A0000h or B0000h while accessing the frame buffer on PCI The SMRAM Enable bit in the DRAM Control
Register must be 1 to enable the features defined by this register Register bits 5 3 apply only when segment
A0000-AFFFFh or B0000-BFFFFh are selected
Bits
Description
7 6 RESERVED
5 OPEN SMRAM SPACE (OSS) When OSS^e1 the CPU can access SMM space without being in
SMM mode That is accesses to SMM space are permitted even with SMIACT negated This bit is
intended to be used during POST to allow the CPU to initialize SMRAM space before the first SMI
interrupt is issued
4 CLOSE SMRAM SPACE (CSS) When CSS^e1 and SMRAM is enabled CPU code accesses to the
SMM memory range are directed to SMM space in main memory and data accesses are forwarded to
PCI This bit allows the CPU to read and write the frame buffer on PCI while executing SMM code
When CSS^e0 and SMRAM is enabled all accesses to the SMRAM memory range both code and
data are directed to SMRAM (main memory)
3 LOCK SMRAM SPACE (LSS) When LSS^e1 this bit prevents the SMM space from being manually
opened effectively disabling bit 5 of this register Only a power-on reset can set this bit to 0
2 0 SMM BASE SEGMENT (SBS) This field defines the 64 KByte base segment where SMM space is
located The memory that is defined by this field is non-cacheable
Bits 2 0
000
001
010
011
SMRAM Location
Top of main memory
Reserved
A0000 – AFFFFh
B0000 – BFFFFh
Bits 2 0
100
101
110
111
SMRAM Location
Reserved
Reserved
Reserved
Reserved
3 2 25 MSG MEMORY SPACE GAP REGISTER
Address Offset
Default Value
Attribute
Size
78-79h
00h
Read Write
16 bits
The Memory Space Gap Register defines the starting address and size of a gap in main memory This register
accommodates ISA devices that have their memory mapped into the 1 MByte – 15 5 MByte range (e g an ISA
LAN card or an ISA frame buffer) The Memory Space Gap Register defines a hole in main memory that
transfers the cycles in this address space to the PCI Bus instead of main memory This area is not cacheable
The memory space gap starting address must be a multiple of the memory space gap size For example a
2 MByte gap must start at 2 4 6 8 10 12 or 14 MBytes
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