82434LX Datasheet, PDF (66/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
The RE and WE bits for each region are used to
shadow BIOS ROM in main memory for improved
system performance To shadow a BIOS area RE is
reset to 0 and WE is set to 1 RE is set to 1 and WE
is reset to 0 Any writes to the BIOS area are for-
warded to PCI
4 4 I O Address Map
I O devices (other than the PCMC) are not support-
ed on the Host Bus The PCMC generates PCI Bus
cycles for all CPU I O accesses except to the
PCMC internal registers Figure 11 shows the map-
ping for the CPU I O address space For the
82434LX three PCMC registers are located in the
CPU I O address space the Configuration Space
Enable (CSE) Register the Turbo-Reset Control
(TRC) Register and the Forward (FORW) Register
290479 – 13
NOTES
1 This 82434NX register is only visible when configuration access mechanism 1 is enabled (via bit 31 of the CON-
FADD Register) Otherwise this I O range is in PCI I O space
2 This 82434NX register is accessed during Dword read writes to 0CF8h Byte or word cycles access the correspond-
ing 8-bit registers even if configuration access mechanism 1 is enabled
Figure 11 CPU I O Address Map
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