82434LX Datasheet, PDF (75/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
When CALE is asserted HA 18 7 flow through the
address latch When CALE is negated the address is
captured in the latch allowing the processor to pipe-
line the next bus cycle onto the address bus Two
copies of CA 6 3 COE CADS and CADV are
provided to reduce capacitive loading Both copies
should be used when the second level cache is im-
plemented with eight 32K x 8 or 32K x 9 SRAMs
Either both copies or only one copy can be used
with 64K x 18 or 64K x 16 SRAMs as determined by
the system board layout and timing analysis The
two copies are always driven to the same logic level
CAA 4 3 and CAB 4 3 are used to count through
the Pentium processor burst order when standard
SRAMs are used to implement the cache
With burst SRAMs the address counting is provided
inside the SRAMs In this case CAA 4 3 and
CAB 4 3 are only used at the beginning of a cycle
to load the initial low order address bits into the
burst SRAMs During CPU accesses host address
lines 6 and 5 are propagated to the CAA 6 5 and
CAB 6 5 lines and are internally latched When a
CPU read cycle forces a line replacement in the sec-
ond level cache all modified lines within the ad-
dressed sector are written back to main memory
The PCMC uses CAA 6 5 and CAB 6 5 to select
among the lines within the sector The Cache Output
Enables (COE 1 0 ) are asserted to enable the
SRAMs to drive data onto the host data bus The
Cache Write Enables (CWE 7 0 ) allow byte con-
trol during CPU writes to the second level cache
An asynchronous SRAM 512-KByte cache can be
implemented with two different types of SRAM byte
control Figure 15 depicts the PCMC connections to
a 512 KByte cache using 64K x 18 SRAMs or 64K x
16 SRAMs with two write enables per SRAM Each
SRAM has a high and low write enable Figure 16
depicts the PCMC connections to a 512-KByte
cache using 64K x 18 SRAMs or 64K x 16 SRAMs
with two byte select lines per SRAM Each SRAM
has a high and low byte select
The type of cache byte control (write enable or byte
select) is programmed in the Cache Byte Control bit
in the Secondary Cache Control Register at configu-
ration space offset 52h When this bit is set to 0
byte select control is used In this mode the
CBS 7 0 lines are multiplexed onto pins 90 91
and 95-100 and CR W 1 0 pins are multiplexed
onto pins 93 and 94 When this bit is set to 1 byte
write enable control is used In this mode the
CWE 7 0 lines are multiplexed onto pins 90 91
and 95-100 CADS 1 0 and CADV 1 0 are only
used with burst SRAMs The Cache Address
Strobes (CADS 1 0 ) are asserted to cause the
burst SRAMs to latch the cache address at the be-
ginning of a second level cache access
CADS 1 0 can be connected to either ADSP or
ADSC on the SRAMs The Cache Advance signals
(CADV 1 0 ) are asserted to cause the burst
SRAMs to advance to the next address of the burst
sequence
5 1 1 CLOCK LATENCIES (82434LX)
Table 5 and Table 6 list the latencies for various
CPU transfers to or from the second level cache for
standard SRAMs and burst SRAMs Standard
SRAM access times of 12 ns and 15 ns are recom-
mended for 66 MHz and 60 MHz operation respec-
tively Burst SRAM clock access times of 8 ns and
9 ns are recommended for 66 MHz and 60 MHz op-
eration respectively Precise SRAM timing require-
ments should be determined by system board elec-
trical simulation with SRAM I O buffer models
Table 5 Second Level Cache Latencies with Standard SRAM (82434LX)
Cycle Type
HCLK Count
Burst Read
3-2-2-2
Burst Write
4-2-2-2
Single Read
3
Single Write
4
Pipelined Back to Back Burst Reads
3-2-2-2 3-2-2-2
Burst Read followed by Pipelined Write
3-2-2-2 4
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