82434LX Datasheet, PDF (25/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
Signal
FRAME
IRDY
TRDY
DEVSEL
STOP
Type
Description
sts
CYCLE FRAME FRAME is driven by the current bus master to indicate the
beginning and duration of an access FRAME is asserted to indicate that a bus
transaction is beginning While FRAME is asserted data transfers continue When
FRAME is negated the transaction is in the final data phase FRAME is an output
of the PCMC during CPU cycles which are directed to PCI FRAME is an input to the
PCMC when the PCMC acts as a slave
sts
INITIATOR READY The assertion of IRDY indicates the current bus master’s ability
to complete the current data phase IRDY works in conjunction with TRDY to
indicate when data has been transferred On PCI data is transferred on each clock
that both IRDY and TRDY are asserted During read cycles IRDY is used to
indicate that the master is prepared to accept data During write cycles IRDY is used
to indicate that the master has driven valid data on the AD 31 0 lines Wait states are
inserted until both IRDY and TRDY are asserted together IRDY is an output of
the PCMC when the PCMC is the PCI master IRDY is an input to the PCMC when
the PCMC acts as a slave
sts
TARGET READY TRDY indicates the target device’s ability to complete the current
data phase of the transaction It is used in conjunction with IRDY A data phase is
completed on each clock that TRDY and IRDY are both sampled asserted During
read cycles TRDY indicates that valid data is present on AD 31 0 lines During write
cycles TRDY indicates the target is prepared to accept data Wait states are
inserted on the bus until both IRDY and TRDY are asserted together TRDY is an
output of the PCMC when the PCMC is the PCI slave TRDY is an input to the PCMC
when the PCMC is a master
sts
DEVICE SELECT When asserted DEVSEL indicates that the driving device has
decoded its address as the target of the current access DEVSEL is an output of the
PCMC when PCMC is a PCI slave and is derived from the MEMCS input MEMCS
is generated by the expansion bus bridge as a decode to the main memory address
space During CPU-to-PCI cycles DEVSEL is an input It is used to determine if any
device has responded to the current bus cycle and to detect a target abort cycle
Master-Abort termination results if no subtractive decode agent exists in the system
and no one asserts DEVSEL within a programmed number of clocks
sts
STOP STOP indicates that the current target is requesting the master to stop the
current transaction This signal is used in conjunction with DEVSEL to indicate
disconnect target-abort and retry cycles When PCMC is acting as a master on PCI if
STOP is sampled active on a rising edge of PCLKIN FRAME is negated within a
maximum of 3 clock cycles STOP may be asserted by the PCMC in three cases If a
PCI master attempts to access main memory when another PCI master has locked
main memory the PCMC asserts STOP to signal retry The PCMC detects this
condition when sampling FRAME and LOCK both active during an address phase
When a PCI master is reading from main memory the PCMC asserts STOP when the
burst cycle is about to cross a cache line boundary When a PCI master is writing to
main memory the PCMC asserts STOP upon filling either of the two PCI-to-main
memory posted write buffers Once asserted STOP remains asserted until FRAME
is negated
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