82434LX Datasheet, PDF (46/191 Pages) Intel Corporation – PCI, CACHE AND MEMORY CONTROLLER PCMC

82434LX 82434NX
3 2 13 DFC DETURBO FREQUENCY CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
51h
80h
Read Write
8 bits
Some software packages rely on the operating speed of the processor to time certain system events To
maintain backward compatibility with these software packages the PCMC provides a mechanism to emulate a
slower operating speed This emulation is achieved with the PCMC’s deturbo mode The deturbo mode is
enabled and disabled via the DM bit in the Turbo-Reset Control Register When the deturbo mode is enabled
the PCMC periodically asserts AHOLD to slow down the effective speed of the CPU The duty cycle of the
AHOLD active period is controlled by the DFC Register
Bits
Description
7 6 DETURBO MODE FREQUENCY ADJUSTMENT VALUE This 8-bit value effectively defines the duty
cycle of the AHOLD signal DFC 7 6 are programmable and DFC 5 0 are 0 The value programmed
into this register is compared against a free running 8-bit counter running at the CPU clock When
the counter is greater than the value specified in this register AHOLD is asserted AHOLD is negated
when the counter value is equal to or smaller than the contents of this register AHOLD is negated
when the counter rolls over to 00h The deturbo emulation speed is directly proportional to the value
in this register Smaller values in this register yield slower deturbo emulation speed The value of 00h
is reserved
5 0 RESERVED
3 2 14 SCC SECONDARY CACHE CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
52h
SSS01R10 (82434LX)
SSS01010 (82434NX)
(S^eStrapping option)
Read Write
8 bits
This 8-bit register defines the secondary cache operations The SCC Register enables and disables the
second level cache adjusts cache size selects the cache write policy and defines the cache SRAM type
After hard reset SCC 7 5 contain the opposite of the signal levels sampled on the Host address lines
A 31 29
Bits
Description
7 6 SECONDARY CACHE SIZE (SCS) This field defines the size of the second level cache The values
sampled on the A 31 30 lines at the rising edge of the PWROK signal are inverted and stored in this
field
Bits 7 6
00
01
10
11
Secondary Cache Size
Cache not populated
Reserved
256-KBytes
512-KBytes
46