MC68LC040RC25A Datasheet, PDF (98/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
4.7.1 Instruction Cache
The IU uses the instruction cache to store instruction prefetches as it requests them.
Instruction prefetches are normally requested from sequential memory locations except
when a change of program flow occurs (e.g., a branch taken) or when an instruction that
can modify the status register (SR) is executed, in which case the instruction pipe is
automatically flushed and refilled. The instruction cache supports a line-based protocol
that allows individual cache lines to be in either the invalid or valid states.
For instruction prefetch requests that hit in the cache, the half-line selected by physical
address bit 3 is multiplexed onto the internal instruction data bus. When an access misses
in the cache, the cache controller requests the line containing the required data from
memory and places it in the cache. If available, an invalid line is selected and updated
with the tag and data from memory. The line state then changes from invalid to valid by
setting the V-bit. If all lines in the set are already valid, a pseudo-random replacement
algorithm is used to select one of the four cache lines replacing the tag and data contents
of the line with the new line information. Figure 4-5 illustrates the instruction-cache line
state transitions resulting from processor and snoop controller accesses. Transitions are
labeled with a capital letter, indicating the previous state, followed by a number indicating
the specific case listed in Table 4-3.
I3–CINV/CPUSH
V1–CPU READ MISS
V2–CPU READ HIT
INVALID
I1-CPU READ MISS
VALID
V3–CINV/CPUSH
V5–SNOOP READ HIT
V6–SNOOP WRITE HIT
Figure 4-5. Instruction-Cache Line State Diagram
4-14
M68040 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA