MC68LC040RC25A Datasheet, PDF (36/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 1-4. Instruction Set Summary (Continued)
Opcode
BTST
Operation
–(bit number of Destination) ø Z;
CAS
CAS2
CHK
CHK2
CINV
CLR
CMP
CMPA
CMPI
CMPM
CMP2
CPUSH
DBcc
DIVS, DIVSL
CAS Destination – Compare Operand ø cc;
if Z, Update Operand ø Destination
else Destination ø Compare Operand
CAS2 Destination 1 – Compare 1 ø cc;
if Z, Destination 2 – Compare ø cc;
if Z, Update 1 ø Destination 1;
Update 2 ø Destination 2
else Destination 1 ø Compare 1;
Destination 2 ø Compare 2
If Dn < 0 or Dn > Source
then TRAP
If Rn < LB or If Rn > UB
then TRAP
If supervisor state
then invalidate selected cache lines
else TRAP
0 ø Destination
Destination – Source ø cc
Destination – Source
Destination – Immediate Data
Destination – Source ø cc
Compare Rn < LB or Rn > UB
and Set Condition Codes
If supervisor state
then if data cache push selected dirty data
cache lines; invalidate selected cache lines
else TRAP
If condition false
then (Dn–1 ø Dn;
If Dn ≠ –1
then PC + dn ø PC)
Destination ÷ Source ø Destination
DIVU, DIVUL Destination ÷ Source ø Destination
EOR
EORI
EORI to CCR
EORI to SR
Source ⊕ Destination ø Destination
Immediate Data ⊕ Destination ø Destination
Source ⊕ CCR ø CCR
If supervisor state
then Source ⊕ SR ø SR
else TRAP
Syntax
BTST Dn,<ea>
BTST #<data>,<ea>
CAS Dc,Du,<ea>
CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–(Rn2)
CHK <ea>,Dn
CHK2 <ea>,Rn
CINVL <caches>, (An)
CINVP <caches>, (An)
CINVA <caches>
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI #<data>,<ea>
CMPM (Ay)+,(Ax)+
CMP2 <ea>,Rn
CPUSHL <caches>, (An)
CPUSHP <caches>, (An)
CPUSHA <caches>
DBcc Dn,<label>
DIVS.W <ea>,Dn
DIVS.L <ea>,Dq
DIVS.L <ea>,Dr:Dq
DIVSL.L <ea>,Dr:Dq
DIVU.W <ea>,Dn
DIVU.L <ea>,Dq
DIVU.L <ea>,Dr:Dq
DIVUL.L <ea>,Dr:Dq
EOR Dn,<ea>
EORI #<data>,<ea>
EORI #<data>,CCR
EORI #<data>,SR
32 ÷ 16 ø 16r:16q
32 ÷ 32 ø 32q
64 ÷ 32 ø 32r:32q
32 ÷ 32 ø 32r:32q
32 ÷ 16 ø 16r:16q
32 ÷ 32 ø 32q
64 ÷ 32 ø 32r:32q
32 ÷ 32 ø 32r:32q
MOTOROLA
M68040 USER’S MANUAL
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