MC68LC040RC25A Datasheet, PDF (52/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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logical address bits. If the translation is resident, the MMU provides the physical address
to the cache controller, which determines if the instruction or data being accessed is
cached. The cache controller uses the lower address bits to index into memory. An
external bus cycle is performed only when explicitly requested by the cache controller.
When the translation is not in the ATC, the MMU searches the translation tables in
memory for the translation information. Microcode and dedicated logic perform the
address calculations and bus cycles required for this search.
3.1 MEMORY MANAGEMENT PROGRAMMING MODEL
The memory management programming model is part of the supervisor programming
model for the M68040. The eight registers that control and provide status information for
address translation in the M68040 are: the user root pointer register (URP), the supervisor
root pointer register (SRP), the translation control register (TCR), four independent
transparent translation registers (ITT0, ITT1, DTT0, and DTT1), and the MMU status
register (MMUSR). Only programs that execute in the supervisor mode can directly
access these registers. Figure 3-2 illustrates the memory management programming
model.
31
0
URP
USER ROOT POINTER REGISTER
31
0
SRP
SUPERVISOR ROOT POINTER REGISTER
15
0
TCR
TRANSLATION CONTROL REGISTER
31
0
DTTR0
DATA TRANSPARENT TRANSLATION REGISTER 0
31
0
DTTR1
DATA TRANSPARENT TRANSLATION REGISTER 1
31
0
ITTR0
INSTRUCTION TRANSPARENT TRANSLATION
REGISTER 0
31
0
ITTR1
INSTRUCTION TRANSPARENT TRANSLATION
REGISTER 1
31
0
MMUSR
MMU STATUS REGISTER
Figure 3-2. Memory Management Programming Model
3.1.1 User and Supervisor Root Pointer Registers
The SRP and URP registers each contain the physical address of the translation table’s
root, which the MMU uses for supervisor and user accesses, respectively. The URP points
to the translation table for the current user task. When a new task begins execution, the
operating system typically writes a new root pointer to the URP. A new translation table
address implies that the contents of the ATCs may no longer be valid. A PFLUSH
instruction should be executed to flush the ATCs before loading a new root pointer value,
if necessary. Figure 3-3 illustrates the format of the 32-bit URP and SRP registers. Bits 8–
MOTOROLA
M68040 USER'S MANUAL
3-3
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