MC68LC040RC25A Datasheet, PDF (55/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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CM—Cache Mode
This field selects the cache mode and access serialization as follows:
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
Section 4 Instruction and Data Caches provides detailed information on caching
modes, and Section 7 Bus Operation provides information on serialization.
W—Write Protect
This bit indicates if the transparent block is write protected. If set, write and read-modify-
write accesses are aborted as if the resident bit in a table descriptor were clear.
0 = Read and write accesses permitted
1 = Write accesses not permitted
3.1.4 MMU Status Register
The MMUSR is a 32-bit register that contains the status information returned by execution
of the PTEST instruction. The PTEST instruction searches the translation tables to
determine status information about the translation of a specified logical address. Transfers
to and from the MMUSR are long-word transfers. The fields of the MMUSR are defined
following Figure 3-6, which illustrates the MMUSR.
31
12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSICAL ADDRESS
B G U1 U 0 S C M M O W T R
Figure 3-6. MMU Status Register Format
Physical Address
This 20-bit field contains the upper bits of the translated physical address. Merging
these bits with the lower bits of the logical address forms the actual physical address.
Bit 12 is undefined if a PTEST is executed with 8-Kbyte pages selected.
B—Bus Error
The B-bit is set if a transfer error is encountered during the table search for the PTEST
instruction. If the B-bit is set, all other bits are zero.
G—Global
This bit is set if the G-bit is set in the page descriptor.
U1, U0—User Page Attributes
These bits are set if corresponding bits in the page descriptor are set.
3-6
M68040 USER'S MANUAL
MOTOROLA
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