MC68LC040RC25A Datasheet, PDF (380/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
MC68EC040 REV2.3 (01/31/2000)
ADDRESS
BUS
DATA
BUS
TRANSFER
MASTER
TRANSFER
CONTROL
SLAVE
TRANSFER
CONTROL
A31–A0
D31–D0
TT0
TT1
TM0
TM1
TM2
TLN0
TLN1
UPA0
UPA1
R/W
SIZ0
SIZ1
LOCK
LOCKE
CIOUT
TS
TIP
TA
TEA
TCI
TBI
MC68EC040
SC0
SC1
MI
BR
BG
BB
CDIS
RSTI
RSTO
MDIS
PL0
PL1
PL2
IPEND
AVEC
PST0
PST1
PST2
PST3
BCLK
PCLK
JS0
TCK
TMS
TDI
TDO
TRST
V_CC
GND
BUS SNOOP CONTROL
AND RESPONSE
BUS ARBITRATION
PROCESSOR
CONTROL
INTERRUPT
CONTROL
STATUS AND
CLOCKS
TEST
POWER SUPPLY
Figure B-3. MC68EC040 Functional Signal Groups
Test Access Port (JTAG) for details concerning IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
B.3 ACCESS CONTROL UNITS
The information in this section replaces the information in Section 3 Memory Management
Unit (Except MC68EC040 and MC68EC040V). When reading Section 4 Instruction and
Data Caches, disregard any references to the MMU; remember the functionality of the
access control registers has replaced that of transparent translation registers. The
MC68EC040 contains two independent ACUs, one for instructions and one for data. Each
ACU allows memory selections to be made requiring attributes particular to peripherals,
shared memory, or other special memory requirements. The following paragraphs describe
the ACUs and the access control registers contained in them.
B-4
M68040 USER’S MANUAL
MOTOROLA
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